公开(公告)号：US20080001620A1

公开(公告)日：2008-01-03

申请号：US11427798

申请日：2006-06-30

Applicant: Fen Chen ,  Kai D. Feng ,  Robert J. Gauthier ,  Tom C. Lee

Inventor： Fen Chen ,  Kai D. Feng ,  Robert J. Gauthier ,  Tom C. Lee

IPC: H03K19/003

CPC classification number: H03K19/018571

Abstract: A method for trimming impedance matching devices in high-speed circuits includes determining an electrical parameter associated with a first tantalum nitride (TaN) resistor used as an impedance matching device in the circuit under test, and comparing the determined electrical parameter associated with the first TaN resistor to a desired design value of the electrical parameter. The resistance value of the first TaN resistor is altered by application of a trimming voltage thereto, wherein the trimming voltage is based on a voltage-resistance characteristic curve of the first TaN resistor. It is then determined whether the altered resistance value of the first TaN resistor causes the electrical parameter to equal the desired design value thereof, and the altering of the resistance value of the first TaN resistor by application of a trimming voltage is repeated until the electrical parameter equals the desired design value thereof.

Abstract translation: 一种用于微调高速电路中的阻抗匹配装置的方法包括：确定与在被测电路中用作阻抗匹配装置的第一氮化钽（TaN）电阻相关联的电参数，并将确定的与第一TaN相关的电参数进行比较 电阻到所需的电参数设计值。 通过施加微调电压来改变第一TaN电阻器的电阻值，其中微调电压基于第一TaN电阻器的耐电压特性曲线。 然后确定第一TaN电阻器的改变的电阻值是否使电参数等于其期望的设计值，并且重复通过施加微调电压来改变第一TaN电阻器的电阻值，直到电参数 等于其期望的设计值。

公开(公告)号：US07064409B2

公开(公告)日：2006-06-20

申请号：US10605885

申请日：2003-11-04

Applicant: Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

Inventor： Dinesh A. Badami ,  Tom C. Lee ,  Baozhen Li ,  Gerald Matusiewicz ,  William T. Motsiff ,  Christopher D. Muzzy ,  Kimball M. Watson ,  Jean E. Wynne

IPC: H01L29/00

CPC classification number: H01L23/5258 ,  H01L23/525 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for fabricating a laser fuse and a method for programming the laser fuse. The laser fuse includes a first dielectric layer having two vias filled with a first self-passivated electrically conducting material. A fuse link is on top of the first dielectric layer. The fuse link electrically connects the two vias and includes a second material having a characteristic of changing its electrical resistance after being exposed to a laser beam. Two mesas are over the fuse link and directly over the two vias. The two mesas each include a third self-passivated electrically conducting material. The laser fuse is programmed by directing a laser beam to the fuse link. The laser beam is controlled such that, in response to the impact of the laser beam upon the fuse link, the electrical resistance of the fuse link changes but the fuse link is not blown off. Such electrical resistance change is sensed and converted to digital signal.

Abstract translation: 用于制造激光熔丝的方法和结构以及用于编程激光熔丝的方法。 激光熔丝包括具有填充有第一自钝化导电材料的两个通孔的第一介电层。 熔丝连接在第一电介质层的顶部。 熔断体将两个通孔电连接并且包括具有在暴露于激光束之后改变其电阻的特性的第二材料。 两个台面位于熔丝链上方，直接穿过两个通孔。 两个台面各自包括第三自钝化导电材料。 激光熔丝通过将激光束引导到熔丝链来编程。 控制激光束，使得响应于激光束对熔丝链的影响，熔丝链的电阻改变，但熔丝链不会被吹掉。 这种电阻变化被检测并转换成数字信号。

公开(公告)号：US08822993B2

公开(公告)日：2014-09-02

申请号：US13550813

申请日：2012-07-17

Applicant: Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/48 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/2858 ,  H01L22/30 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.

Abstract translation: 一种集成电路（IC）及其制造方法。 在一个实施例中，集成电路包括：基板; 第一金属层，设置在所述基板上并且包括被构造为指示所述集成电路的一部分中的裂纹的传感器结构; 以及设置在所述第一金属层附近的第二金属层，所述第二金属层包括靠近所述传感器结构设置的导线部件。

公开(公告)号：US08669146B2

公开(公告)日：2014-03-11

申请号：US13005560

申请日：2011-01-13

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L21/336

CPC classification number: H01L29/0688 ,  H01L27/0266 ,  H01L29/0615 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

Abstract: A method of forming a semiconductor structure, including forming a channel in a first portion of a semiconductor layer and forming a doped extension region in a second portion of the semiconductor layer abutting the channel on a first side and abutting an insulator material on a bottom side. The first portion of the semiconductor layer is thicker than the second portion of the semiconductor layer.

公开(公告)号：US20140021469A1

公开(公告)日：2014-01-23

申请号：US13550813

申请日：2012-07-17

Applicant: Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee

Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Tom C. Lee

IPC: H01L23/48 ,  H01L21/66

CPC classification number: H01L22/34 ,  G01R31/2858 ,  H01L22/30 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.

Abstract translation: 一种集成电路（IC）及其制造方法。 在一个实施例中，集成电路包括：基板; 第一金属层，设置在所述基板上并且包括被构造为指示所述集成电路的一部分中的裂纹的传感器结构; 以及设置在所述第一金属层附近的第二金属层，所述第二金属层包括靠近所述传感器结构设置的导线部件。

公开(公告)号：US20130141823A1

公开(公告)日：2013-06-06

申请号：US13312047

申请日：2011-12-06

Applicant: James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

Inventor： James P. Di Sarro ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra

IPC: H02H9/04 ,  G06F17/50

CPC classification number: H02H9/046

Abstract: Methods for responding to an electrostatic discharge (ESD) event on a voltage rail, ESD protection circuits, and design structures for an ESD protection circuit. An RC network of the ESD protection circuit includes a capacitor coupled to a field effect transistor at a node. The node of the RC network is coupled with an input of the inverter. The field-effect transistor is coupled with an output of the inverter. In response to an ESD event, a trigger signal is supplied from the RC network to the input of the inverter, which drives a clamp device to discharge current from the ESD event from the voltage rail. An RC time constant of the RC network is increased in response to the ESD event to sustain the discharge of the current by the clamp device.

Abstract translation: 用于响应电压轨上的静电放电（ESD）事件，ESD保护电路以及ESD保护电路的设计结构的方法。 ESD保护电路的RC网络包括耦合到节点处的场效应晶体管的电容器。 RC网络的节点与逆变器的输入端相连。 场效应晶体管与反相器的输出端相连。 响应于ESD事件，触发信号从RC网络提供给逆变器的输入，该驱动器驱动钳位装置以从ESD电压放电来自电压轨。 响应于ESD事件，RC网络的RC时间常数增加以维持钳位装置的电流放电。

公开(公告)号：US08288747B2

公开(公告)日：2012-10-16

申请号：US12842158

申请日：2010-07-23

Applicant: Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

Inventor： Fen Chen ,  Richard Steven Kontra ,  Tom C. Lee ,  Theodore M. Levin ,  Christopher David Muzzy ,  Timothy Dooling Sullivan

IPC: H01L29/00 ,  H01L47/00

CPC classification number: G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

Abstract: A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.

Abstract translation: 一个结构。 该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。 电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。 电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

公开(公告)号：US20120153434A1

公开(公告)日：2012-06-21

申请号：US12969004

申请日：2010-12-15

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  Anthony K. Stamper

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/82 ,  H01L23/5223 ,  H01L27/0207 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes.

Abstract translation: 金属绝缘体金属（MIM）电容器和制造MIM电容器的方法。 MIM电容器包括层间绝缘层（ILD）层，其中各孔由多个侧壁限定，并且各自从ILD层的顶表面延伸到第一层间电介质层。 布置在孔的侧壁和ILD层的顶表面上的层叠层包括底部导电电极，顶部导电电极和位于底部和顶部导电电极之间的电容器电介质。

公开(公告)号：US20120146179A1

公开(公告)日：2012-06-14

申请号：US12967308

申请日：2010-12-14

Applicant: Tom C. Lee ,  Thomas L. McDevitt ,  William J. Murphy

Inventor： Tom C. Lee ,  Thomas L. McDevitt ,  William J. Murphy

IPC: H01L23/62 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.

Abstract translation: 电熔丝和形成电熔丝的方法。 电熔丝包括通过图案化由第一导电材料构成的第一层并且设置在电介质层的顶表面上而形成的电流分流器。 在电流分路上形成层叠层，并且在电流分路周围形成介电层的顶表面。 层叠包括由第二导电材料构成的第二层和由第三导电材料构成的第三层。 层叠体可以被图案化以限定作为层叠体的第一部分的熔丝链，其直接接触电介质层的顶表面，并且通过电流分路与端子作为与电介质层的顶表面分离的第二部分。

公开(公告)号：US20120012976A1

公开(公告)日：2012-01-19

申请号：US12838850

申请日：2010-07-19

Applicant: Jeffrey P. Gambino ,  Tom C. Lee ,  Kevin G. Petrunich ,  David C. Thomas

Inventor： Jeffrey P. Gambino ,  Tom C. Lee ,  Kevin G. Petrunich ,  David C. Thomas

IPC: H01L29/86 ,  G06F9/45 ,  H01L21/326 ,  H01L21/02

CPC classification number: H01L27/11206 ,  H01L23/5258 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.

Abstract translation: 本公开一般涉及熔丝结构，其形成和编程的方法，更具体地涉及具有裂纹停止空隙的熔断结构。 熔丝结构包括其上具有介电层的半导体衬底和裂纹阻挡空隙。 电介质层包括至少一个熔断器，裂纹阻挡空隙与保险丝的两个相对的两侧相邻，并且比底表面和保险丝顶表面之上延伸。 本公开还涉及上述的设计结构。