公开(公告)号：US06909583B2

公开(公告)日：2005-06-21

申请号：US10437090

申请日：2003-05-13

申请人： Min Li ,  Simon H. Liao ,  Masashi Sano ,  Kiyoshi Noguchi ,  Kochan Ju ,  Cheng T. Horng

发明人： Min Li ,  Simon H. Liao ,  Masashi Sano ,  Kiyoshi Noguchi ,  Kochan Ju ,  Cheng T. Horng

IPC分类号： G01R33/09 ,  G11B5/39 ,  G11B5/127

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R33/093 ,  G11B5/3903 ,  Y10T29/49034 ,  Y10T29/49044 ,  Y10T29/49046

摘要： A method for forming a bottom spin valve sensor having a synthetic antiferromagnetic pinned (SyAP) layer, antiferromagnetically coupled to a pinning layer, in which one of the layers of the SyAP is formed as a three layer lamination that contains a specularly reflecting oxide layer of FeTaO. The sensor formed according to this method has an extremely high GMR ratio and exhibits good pinning strength.

摘要翻译： 一种用于形成底部自旋阀传感器的方法，该底部自旋阀传感器具有反结合磁耦合到钉扎层的合成反铁磁钉扎（SyAP）层，其中SyAP的一个层形成为三层层压，其包含镜面反射氧化物层 FeTaO。 根据该方法形成的传感器具有非常高的GMR比，并且具有良好的钉扎强度。

公开(公告)号：US06517896B1

公开(公告)日：2003-02-11

申请号：US09633768

申请日：2000-08-07

申请人： Cheng T. Horng ,  Mao-Min Chen ,  Min Li ,  Ru-Ying Tong

发明人： Cheng T. Horng ,  Mao-Min Chen ,  Min Li ,  Ru-Ying Tong

IPC分类号： B05D512

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11B5/3163 ,  G11B5/3903 ,  H01F10/324 ,  H01F10/3272 ,  H01F10/3295 ,  H01F41/302 ,  H01F41/325 ,  Y10T29/49034 ,  Y10T29/49044

摘要： A high performance specular free layer bottom spin valve is disclosed. This structure made up the following layers: NiCr/MnPt/CoFe/Ru/CoFe/Cu/free layer/Cu/Ta or TaO/Al2O3. A key feature is that the free layer is made of a very thin CoFe/NiFe composite layer. Experimental data confirming the effectiveness of this structure is provided, together with a method for manufacturing it and, additionally, its longitudinal bias leads.

公开(公告)号：US06307721B1

公开(公告)日：2001-10-23

申请号：US09148558

申请日：1998-09-04

申请人： Mao-Min Chen ,  Cherng-Chyi Han ,  Cheng T. Horng

发明人： Mao-Min Chen ,  Cherng-Chyi Han ,  Cheng T. Horng

IPC分类号： G11B539

CPC分类号： G11B5/3954 ,  G11B5/3903

摘要： A magnetoresistive (MR) sensor element and a method for fabricating the magnetoresistive (MR) sensor element. There is first provided a substrate. There is then formed over the substrate a first shield layer. There is then formed upon the first shield layer a first dielectric spacer layer. There is then formed upon the first dielectric spacer layer a patterned magnetoresistive (MR) layer. There is then formed adjacent to and electrically communicating with a pair of opposite ends of the patterned magnetoresistive (MR) layer a pair of patterned conductor lead layers to define a trackwidth of the patterned magnetoresistive (MR) layer. There is then formed upon the pair of patterned conductor lead layers and upon the patterned magnetoresistive (MR) layer at the trackwidth of the patterned magnetoresistive (MR) layer a blanket second dielectric spacer layer. Finally, there is then formed upon the blanket second dielectric spacer layer a second shield layer, where a first thickness of the blanket second dielectric spacer layer separating a patterned conductor lead layer within the pair of patterned conductor lead layers from the second shield layer is greater than a second thickness of the blanket second dielectric spacer layer separating the patterned magnetoresistive (MR) layer from the second shield layer within the trackwidth of the patterned magnetoresistive (MR) layer. The method contemplates a magnetoresistive (MR) sensor element fabricated in accord with the method.

摘要翻译： 磁阻（MR）传感器元件和制造磁阻（MR）传感器元件的方法。 首先提供基板。 然后在衬底上形成第一屏蔽层。 然后在第一屏蔽层上形成第一电介质隔离层。 然后在第一电介质隔离层上形成图案化磁阻（MR）层。 然后形成为与图案化磁阻（MR）层的一对相对端相邻并与其电连通一对图案化的导体引线层，以限定图案化磁阻（MR）层的轨道宽度。 然后形成在一对图案化导体引线层上，并且在图案化磁阻（MR）层的轨道宽度处的图案化磁阻（MR）层上形成毯式第二介电隔离层。 最后，然后在第二绝缘间隔层上形成第二屏蔽层，其中第一厚度的第二绝缘隔离层将第一屏蔽层内的图案化导体引线层中的图案化导体引线层分离， 比在图案化磁阻（MR）层的轨道宽度内将图案化磁阻（MR）层与第二屏蔽层分离的第二厚度的第二介电隔离层的厚度。 该方法考虑了根据该方法制造的磁阻（MR）传感器元件。

公开(公告)号：US4303933A

公开(公告)日：1981-12-01

申请号：US98588

申请日：1979-11-29

申请人： Cheng T. Horng ,  Michael R. Poponiak ,  Hans S. Rupprecht ,  Robert O. Schwenker

发明人： Cheng T. Horng ,  Michael R. Poponiak ,  Hans S. Rupprecht ,  Robert O. Schwenker

IPC分类号： H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/04 ,  H01L29/72

CPC分类号： H01L21/743 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/7325 ,  Y10S148/131

摘要： A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.

摘要翻译： 公开的器件制造方法是自对准工艺。 形成的装置具有小的垂直和水平尺寸。 器件区域被具有几乎垂直侧壁的深氧化物沟槽围绕。 深沟槽从外延硅表面通过N +子集电极区域延伸到P衬底中。 深沟的宽度约为2〜3.0亩。 从外延硅表面延伸到N +子集电极的上部的浅氧化物沟槽分离基极和集电极触点。 隔离区域和形成晶体管的硅的表面是共面的。 如图所示。 如图1所示，制造的双极晶体管具有台面型结构。 晶体管基极尺寸仅略大于发射极。 这种小的基极面积导致集电极电容低，这是超高性能集成电路器件中非常重要的参数。 所公开的结构中与晶体管基极的接触是通过围绕发射极的厚的重硼掺杂的多晶硅层实现的，并且与活性基底进行横向接触。

公开(公告)号：US4211582A

公开(公告)日：1980-07-08

申请号：US52997

申请日：1979-06-28

申请人： Cheng T. Horng ,  Robert O. Schwenker

发明人： Cheng T. Horng ,  Robert O. Schwenker

IPC分类号： H01L21/76 ,  H01L21/033 ,  H01L21/263 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306

CPC分类号： H01L21/0337 ,  H01L21/2633 ,  H01L21/3065 ,  H01L21/76208 ,  H01L21/76229 ,  H01L21/768 ,  H01L21/76877 ,  Y10S148/05 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/111 ,  Y10S148/131

摘要： A method for making wide, deep recessed oxide isolation trenches in silicon semiconductor substrates. A semi-conductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizontal and vertical surfaces of the etched structure to a thickness equalling the width of a desired silicon oxide mask. The mask is used for etching multiple deep trenches in the substrate, the trenches being separated by thin walls of silicon. The thickness of the walls is uniformly equal to and determined by the thickness of the deposited silicon oxide mask.The deposited silicon oxide is reactively ion etched away from the horizontal surfaces, leaving the oxide only on the sidewalls of the shallow trenches. The silicon is deeply etched, using the remaining oxide as a mask. Boron is ion implanted and the resulting structure is thermally oxidized sufficiently to completely oxidize the silicon under the deposited oxide mask and to oxidize the silicon surfaces at the bottoms of the trenches. The remaining trench volume is filled in with chemical-vapor-deposited silicon dioxide.

摘要翻译： 一种用于在硅半导体衬底中制造宽的深凹陷氧化物隔离沟槽的方法。 选择性地蚀刻半导体衬底以产生由狭窄的硅台面分开的间隔一连串的窄的浅沟槽。 氧化硅在蚀刻结构的水平和垂直表面上化学气相沉积到等于所需氧化硅掩模宽度的厚度。 掩模用于蚀刻衬底中的多个深沟槽，沟槽被薄壁的硅分隔开。 壁的厚度均匀地等于并由沉积的氧化硅掩模的厚度确定。 沉积的氧化硅被离子蚀刻离开水平表面，仅将氧化物留在浅沟槽的侧壁上。 硅被深刻蚀刻，使用剩余的氧化物作为掩模。 硼离子注入，并且所得结构被充分热氧化以在沉积的氧化物掩模下完全氧化硅，并在沟底部氧化硅表面。 剩余的沟槽体积填充有化学气相沉积的二氧化硅。

公开(公告)号：US20130175644A1

公开(公告)日：2013-07-11

申请号：US13344292

申请日：2012-01-05

申请人： Cheng T. Horng ,  Ru-Ying Tong

发明人： Cheng T. Horng ,  Ru-Ying Tong

IPC分类号： H01L29/82 ,  H01L21/8246 ,  B82Y99/00

CPC分类号： H01L43/12 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3259 ,  H01F10/3272 ,  H01F10/3286 ,  H01F41/305 ,  H01L27/228 ,  H01L43/08

摘要： A STT-RAM MTJ is disclosed with a composite tunnel barrier comprised of a CoMgO layer that contacts a pinned layer and a MgO layer which contacts a free layer. A CoMg layer with a Co content between 20 and 40 atomic % is deposited on the pinned layer and is then oxidized to produce Co nanoconstrictions within a MgO insulator matrix. The nanoconstrictions control electromigration of Co into an adjoining MgO layer. The free layer may comprise a nanocurrent channel (NCC) layer such as FeSiO or a moment dilution layer such as Ta between two ferromagnetic layers. Furthermore, a second CoMgO layer or a CoMgO/MgO composite may serve as a perpendicular Hk enhancing layer formed between the free layer and a cap layer. One or both of the pinned layer and free layer may exhibit in-plane anisotropy or perpendicular magnetic anisotropy.

摘要翻译： 公开了具有由接触被钉扎层的CoMgO层和接触自由层的MgO层组成的复合隧道势垒的STT-RAM MTJ。 将钴含量为20至40原子％的CoMg层沉积在钉扎层上，然后被氧化以在MgO绝缘体基体内产生Co纳米收缩。 纳米监测将Co的电迁移控制到相邻的MgO层中。 自由层可以包括纳米电流通道（NCC）层，例如FeSiO或在两个铁磁层之间的诸如Ta之间的力矩稀释层。 此外，第二CoMgO层或CoMgO / MgO复合物可以用作在自由层和盖层之间形成的垂直Hk增强层。 被钉扎层和自由层中的一个或两个可以表现出面内各向异性或垂直磁各向异性。

公开(公告)号：US08470462B2

公开(公告)日：2013-06-25

申请号：US12927939

申请日：2010-11-30

申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Guenole Jan

发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Guenole Jan

IPC分类号： G11B5/706 ,  H01L43/08 ,  G01R33/09 ,  G11C11/16

CPC分类号： C23C14/3414 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3259 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/3295 ,  H01F41/307 ,  H01L43/08 ,  H01L43/12 ,  Y10T428/1114

摘要： A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation process. A Co10Fe70B20/NCC/Co10Fe70B20, Co10Fe70B20/NCC/Co10Fe70B20/NCC, or Co10Fe70B20/NCC/Co10Fe70B20/NCC/Co10Fe70B20 free layer configuration where NCC is a nanocurrent channel layer made of Fe(20%)-SiO2 is used to minimize Jc0 while enabling higher thermal stability, write voltage, read voltage, Ho, and Hc values that satisfy 64 Mb design requirements. The NCC layer is about 10 Angstroms thick to match the minimum Fe(Si) grain diameter size. The MTJ is annealed with a temperature of about 330° C. to maintain a high magnetoresistive ratio while maximizing Hk⊥(interfacial) for the free layer thereby reducing Heff and lowering the switching current. The Co10Fe70B20 layers are sputter deposited with a low pressure process with a power of about 15 Watts and an Ar flow rate of 40 standard cubic centimeters per minute to lower Heff for the free layer.

摘要翻译： 公开了具有通过自然氧化工艺形成的MgO隧道势垒的STT-RAM MTJ。 使用NCO是由Fe（20％） - SiO 2制成的纳米电流通道层的Co10Fe70B20 / NCC / Co10Fe70B20，Co10Fe70B20 / NCC / Co10Fe70B20 / NCC或Co10Fe70B20 / NCC / Co10Fe70B20 / NCC / Co10Fe70B20 / NCC / Co10Fe70B20自由层配置，以使Jc0最小化 实现满足64Mb设计要求的更高的热稳定性，写电压，读电压，Ho和Hc值。 NCC层的厚度约为10埃，以符合最小Fe（Si）晶粒直径尺寸。 MTJ在约330℃的温度下退火，以保持高的磁阻比，同时使自由层的Hk⊥（界面）最大化，从而降低Heff并降低开关电流。 Co10Fe70B20层用低压工艺溅射沉积，功率约为15瓦，Ar流速为40标准立方厘米每分钟，以降低自由层的Heff。

公开(公告)号：US08372661B2

公开(公告)日：2013-02-12

申请号：US11981127

申请日：2007-10-31

申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jiuh Torng ,  Witold Kula

发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Chyu-Jiuh Torng ,  Witold Kula

IPC分类号： H01L21/00

CPC分类号： H01L43/10 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um2) and a Fe or Fe/CoFeB/Fe free layer which provides a lower intrinsic damping constant than a CoFeB free layer. A Fe, FeB, or Fe/CoFeB/Fe free layer when formed with a MgO tunnel barrier (radical oxidation process) and a CoFeB AP1 pinned layer in a MRAM MTJ stack annealed at 360° C. provides a high dR/R (TMR)>100% and a substantial improvement in read margin with a TMR/Rp_cov=20. High speed measurement of 100 nm×200 nm oval STT-RAM MTJs has shown a Jc0 for switching a Fe free layer is one half that for switching an amorphous CO40Fe40B20 free layer. A Fe/CoFeB/Fe free layer configuration allows the Hc value to be increased for STT-RAM applications.

摘要翻译： 公开了使自旋转移磁化开关电流（Jc）最小化的STT-RAM MTJ。 MTJ具有形成有自然氧化工艺的MgO隧道阻挡层，以实现低的RA（10欧姆 - um2）和不含CoFeB自由层的较低的固有阻尼常数的Fe或Fe / CoFeB / Fe自由层。 当在360℃退火的MRAM MTJ堆叠中形成具有MgO隧道势垒（自由基氧化法）和CoFeB AP1钉扎层的Fe，FeB或Fe / CoFeB / Fe自由层时，提供高dR / R（TMR ）> 100％，TMR / Rp_cov = 20时读取余量大幅度提高。 100 nm×200 nm椭圆STT-RAM MTJ的高速测量显示，用于切换无Fe层的Jc0是用于切换无定形CO40Fe40B20自由层的一半。 Fe / CoFeB / Fe自由层配置允许为STT-RAM应用增加Hc值。

公开(公告)号：US07948044B2

公开(公告)日：2011-05-24

申请号：US12082155

申请日：2008-04-09

申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Yimin Guo

发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Yimin Guo

IPC分类号： H01L29/82

CPC分类号： H01L43/08 ,  H01L43/12 ,  Y10S977/883

摘要： A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R is disclosed. The MTJ has a MgO tunnel barrier formed by natural oxidation to achieve a low RA, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0. There is a thin Ru capping layer for a spin scattering effect. The reference layer has a shape anisotropy and Hc substantially greater than that of the free layer to establish a “self-pinned” state. The free layer, capping layer and hard mask are formed in an upper section of a nanopillar that has an area substantially less than a lower pedestal section which includes a bottom electrode, reference layer, seed layer, and tunnel barrier layer. The reference layer is comprised of an enhanced damping constant material that may be an insertion layer, and the free layer has a low damping constant.

摘要翻译： 公开了一种在实现高dR / R的同时使自旋转移磁化开关电流（Jc）最小化的STT-RAM MTJ。 MTJ具有通过自然氧化形成的MgO隧道势垒以实现低RA，以及具有中间纳米通道层的CoFeB / FeSiO / CoFeB复合自由层以使Jc0最小化。 有一个薄的Ru覆盖层用于自旋散射效应。 参考层具有形状各向异性，并且Hc基本上大于自由层的Hc以形成“自固定”状态。 自由层，覆盖层和硬掩模形成在纳米柱的上部，其具有基本上小于包括底部电极，参考层，种子层和隧道势垒层的下基座部分的面积。 参考层由增强的阻尼常数材料组成，其可以是插入层，并且自由层具有低阻尼常数。

公开(公告)号：US07936539B2

公开(公告)日：2011-05-03

申请号：US11717973

申请日：2007-03-14

申请人： Cheng T. Horng ,  Ru-Ying Tong

发明人： Cheng T. Horng ,  Ru-Ying Tong

IPC分类号： G11B5/39

CPC分类号： G11B5/39 ,  Y10T29/49044

摘要： A bottom spin-valve GMR sensor has been fabricated that has ultra-thin layers of high density and smoothness. In addition, these layers are inherently furnished with sub-monolayer thick oxygen surfactant layers. The sensor is fabricated using a method in which the layers are sputtered in a mixture of Ar and O2. A particularly novel feature of the method is the use of a sputtering chamber with an ultra-low base pressure and correspondingly ultra-low pressure mixtures of Ar and O2 sputtering gas (

摘要翻译： 已经制造了具有高密度和平滑度的超薄层的底部自旋阀GMR传感器。 此外，这些层本质上具有亚单层厚氧表面活性剂层。 传感器使用其中层以Ar和O2的混合物溅射的方法制造。 该方法的一个特别新颖的特征是使用具有超低基础压力的溅射室和相应的Ar和O 2溅射气体（<0.5毫托）的超低压混合物，其中混合的氧气的分压较小 比5×10-9乇。