公开(公告)号：US06775736B2

公开(公告)日：2004-08-10

申请号：US10062812

申请日：2002-01-31

申请人： Louis L. Hsu ,  Rajiv J. Joshi ,  Jeremy K. Stephens ,  Daniel W. Storaska

发明人： Louis L. Hsu ,  Rajiv J. Joshi ,  Jeremy K. Stephens ,  Daniel W. Storaska

IPC分类号： G06F1200

CPC分类号： G11C7/1048 ,  G06F13/4243 ,  G11C5/063 ,  G11C11/4096 ,  G11C29/846 ,  G11C2207/104

摘要： A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths. The data communication system includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths. The data communication system further includes circuitry for controlling the respective one data path in accordance with receipt of a monitor signal indicating that a data transfer operation has been initiated for transfer of data to or from the respective one data path. The circuitry for controlling includes circuitry for generating a control signal for controlling resetting of the respective one data path after data is transferred for preparation of a subsequent data transfer operation.

摘要翻译： 一种具有多个数据路径的宽数据宽度半导体存储器系统的自定时数据通信系统。 数据通信系统包括被配置为存储数据的多个数据库，其中多个数据库中的相应数据库连接到多个数据路径中相应的一个数据路径。 数据通信系统还包括用于根据接收到指示数据传送操作已被启动以用于将数据传送到相应的一个数据路径或从相应的一个数据路径传送数据的监视信号来控制相应的一个数据路径的电路。 用于控制的电路包括用于产生控制信号的电路，该控制信号用于在传送数据以准备随后的数据传送操作之后控制相应的一个数据路径的复位。

公开(公告)号：US06751152B2

公开(公告)日：2004-06-15

申请号：US09999379

申请日：2001-10-31

申请人： Louis L. Hsu ,  Toshiaki K. Kirihata ,  Daniel W. Storaska

发明人： Louis L. Hsu ,  Toshiaki K. Kirihata ,  Daniel W. Storaska

IPC分类号： G11C800

CPC分类号： G11C11/4085 ,  G11C7/065 ,  G11C11/4091

摘要： A memory array architecture employs a full Vdd bitline precharged voltage and a low wordline boost voltage, which is less than Vdd plus the threshold voltage of the access transistor. In a write mode, a first low level of a data bit is almost fully written to a storage element, however a second high level of the data bit is not fully written to the storage element. In a read mode, the first low level of the data bit is fully read out from the storage element, however the second high level of the data bit is not read out by utilizing the access transistor threshold voltage. This allows a sensing signal only with the first voltage level transfer to the Vdd precharged BL. A reference WL is preferably used for generating a reference bitline voltage for a differential Vdd sensing scheme. Alternatively, a single BL digital sensing scheme may be used. Lowering the wordline voltage results in a reduction in power consumption by saving power on Vpp generator and support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving cost.

摘要翻译： 存储器阵列架构采用全Vdd位线预充电电压和低字线升压电压，其小于Vdd加上存取晶体管的阈值电压。 在写入模式中，数据位的第一低电平几乎完全写入存储元件，然而数据位的第二高电平未完全写入存储元件。 在读取模式下，数据位的第一低电平从存储元件完全读出，然而数据位的第二高电平不通过利用存取晶体管阈值电压被读出。 这允许感测信号仅在第一电压电平传输到Vdd预充电BL。 参考WL优选地用于产生用于差分Vdd感测方案的参考位线电压。 或者，可以使用单个BL数字感测方案。 降低字线电压通过节省Vpp发生器和支持电路上的功率以及减小Vpp发生器和支持电路的尺寸而降低功耗，并且消除了与Vpp电压相关的高电压问题，例如介质击穿和其他可靠性 同时避免复杂的解码方案并节省成本。

公开(公告)号：US06697909B1

公开(公告)日：2004-02-24

申请号：US09660431

申请日：2000-09-12

申请人： Li-Kong Wang ,  Louis L. Hsu

发明人： Li-Kong Wang ,  Louis L. Hsu

IPC分类号： G06F1300

CPC分类号： G11C11/40603 ,  G06F12/0802 ,  G11C11/406 ,  G11C11/40607

摘要： A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is performed with respect to a DRAM cache memory by detecting a request address from a processor, stopping a normal refresh operation when the request address is detected, comparing the request address with TAG addresses stored in a TAG memory, generating refresh addresses to refresh data stored in the cache memory, each of which is generated based on an age of data corresponding to the refresh address, and performing a read/write operation on a wordline accessed by the request addresses and refreshing data on wordlines accessed by the refresh addresses, wherein the read/write operation and the refreshing of data are performed simultaneously.

摘要翻译： 提供了一种用于刷新计算机系统中的动态随机存取存储器（DRAM）高速缓冲存储器中的数据的方法和装置，用于执行数据刷新操作而不刷新（例如处理器中的延迟）。 通过检测来自处理器的请求地址，当检测到请求地址时停止正常刷新操作，将请求地址与存储在TAG存储器中的TAG地址进行比较，生成刷新地址 刷新存储在高速缓冲存储器中的数据，其中每个基于与刷新地址相对应的数据的年龄生成，并且对由请求地址访问的字线执行读/写操作，并且通过刷新访问的字线刷新数据 地址，其中同时执行读/写操作和数据刷新。

公开(公告)号：US06683805B2

公开(公告)日：2004-01-27

申请号：US10067411

申请日：2002-02-05

申请人： Rajiv V. Joshi ,  Louis L. Hsu ,  Azeez J. Bhavnagarwala

发明人： Rajiv V. Joshi ,  Louis L. Hsu ,  Azeez J. Bhavnagarwala

IPC分类号： G11C11413

CPC分类号： G11C11/412

摘要： An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.

摘要翻译： 提供一种SRAM系统，其具有包括至少一个接收第一电源电压的电池的SRAM单元阵列和用于向至少一个电路的至少一个选定电路提供第二电源电压的功率控制电路。 该系统是存储器阵列和逻辑系统之一，并且至少一个电路的电路是存储器阵列的存储单元，存储器阵列的读出放大器和逻辑系统的路径之一。 还提供了一种用于向系统的至少一个电路提供电源电压的方法。

公开(公告)号：US06627924B2

公开(公告)日：2003-09-30

申请号：US09845695

申请日：2001-04-30

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L2974

CPC分类号： H01L27/1027 ,  H01L21/8213 ,  H01L27/0605 ,  Y10S438/931

摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

公开(公告)号：US06617702B2

公开(公告)日：2003-09-09

申请号：US09769080

申请日：2001-01-25

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Carl Radens ,  Jack A. Mandelman ,  Tsorng-Dih Yuan

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Carl Radens ,  Jack A. Mandelman ,  Tsorng-Dih Yuan

IPC分类号： H01L23544

CPC分类号： H01L23/48 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0694 ,  H01L2223/54473 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01077 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49133 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.

摘要翻译： 本发明提供了在一个或多个基板的正面和背面上制造或结合到其上的微电子电路系统，例如通信设备和芯片，以提供通过一个或多个基板的电路系统之间的无线通信。 在一个实施例中，位于衬底的相对侧上的两个电路系统被对准以提供通过衬底的两个电路系统之间的无线通信。 在另一个实施例中，位于一个或多个基板上的通信设备被对准以通过一个或多个基板来提供通信设备之间的无线通信。 在另一个实施例中，位于透明基板的相对侧上的两个芯片被对准以提供通过透明基板的两个芯片之间的无线通信。

公开(公告)号：US06512683B2

公开(公告)日：2003-01-28

申请号：US09827071

申请日：2001-04-05

申请人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata

发明人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata

IPC分类号： G11C1500

CPC分类号： G06F12/0895 ,  G06F12/0846 ,  G11C7/1042

摘要： The speed of memories is increased by trading memory density (or area) for speed (or cycle time). An n by n memory array is used to reduce the memory cycle time by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3ns (or n=2) cycle time, a 2 by 2 memory array is used. Or, in order to achieve a 1ns cycle time (or n=6), then a 6 by 6 memory array is used.

摘要翻译： 通过为速度（或循环时间）交易记忆密度（或面积）来提高记忆速度。 n n存储器阵列用于将存储器周期时间减少1 / n。 例如，如果现有存储器周期时间为6ns，为了实现3ns（或n = 2）周期时间，则使用2乘2存储器阵列。 或者，为了实现1ns周期时间（或n = 6），则使用6乘6存储器阵列。

公开(公告)号：US06426914B1

公开(公告)日：2002-07-30

申请号：US09839105

申请日：2001-04-20

申请人： Robert H. Dennard ,  Louis L. Hsu ,  Toshiaki K. Kirihata

发明人： Robert H. Dennard ,  Louis L. Hsu ,  Toshiaki K. Kirihata

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087

摘要： A short cycle DRAM use a floating wordline, dynamic row decoder and bitline VDD precharge, which improves the array efficiency of the short cycle DRAM (3-6 ns) without compromising its performance. A small size wordline driver circuit is provided to reduce the row size of the short cycle DRAM without compromising row access timing. A dynamic decoding operation is implemented which intentionally allows some of the deselected wordlines to float during row access. A Vdd bitline precharge/sensing technique avoids a detrimental (or positive) coupling effect to the floating wordlines during row accessing. A Vdd data-line (or DQ) precharge for a read operation, and control of incoming data timing avoids a detrimental (or positive) coupling effect for a write operation.

摘要翻译： 短周期DRAM使用浮动字线，动态行解码器和位线VDD预充电，这提高了短周期DRAM（3-6ns）的阵列效率，而不损害其性能。 提供了一种小尺寸字线驱动器电路，以减少短周期DRAM的行大小，而不会影响行访问时序。 实现动态解码操作，其有意地允许一些未选择的字线在行访问期间浮动。 Vdd位线预充电/感测技术在行访问期间避免了对浮动字线的有害（或正）耦合效应。 用于读取操作的Vdd数据线（或DQ）预充电以及输入数据时序的控制避免了写入操作的有害（或正）耦合效应。

公开(公告)号：US06410369B1

公开(公告)日：2002-06-25

申请号：US09591511

申请日：2000-06-12

申请人： Roy Childs Flaker ,  Louis L. Hsu ,  Fariborz Assaderaghi ,  Jack A. Mandelman

发明人： Roy Childs Flaker ,  Louis L. Hsu ,  Fariborz Assaderaghi ,  Jack A. Mandelman

IPC分类号： H01L2100

CPC分类号： H01L27/1104 ,  H01L27/1203

摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.

摘要翻译： 绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。 在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。 在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。 最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。

公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。