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428 条记录 (耗时 0.041 秒)

    Nonplanar device with stress incorporation layer and method of fabrication
    51.
    发明授权
    Nonplanar device with stress incorporation layer and method of fabrication 有权
    具有应力结合层的非平面器件及其制造方法

    公开(公告)号：US07241653B2

    公开(公告)日：2007-07-10

    申请号：US11173443

    申请日：2005-06-30

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849

    摘要： A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.

    摘要翻译： 包括具有顶表面和横向相对侧壁的半导体本体的半导体器件形成在绝缘基板上。 栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。 在半导体主体的顶表面上的栅极电介质上形成栅电极，并且与半导体本体的横向相对的侧壁上的栅电介质相邻地形成栅电极。 然后在半导体本体附近形成薄膜，其中薄膜在半导体本体中产生应力。

    CONDUCTIVE OXIDE RANDOM ACCESS MEMORY (CORAM) CELL AND METHOD OF FABRICATING SAME
    54.
    发明申请
    CONDUCTIVE OXIDE RANDOM ACCESS MEMORY (CORAM) CELL AND METHOD OF FABRICATING SAME 有权
    导电氧化物随机存取存储器（CORAM）单元及其制造方法

    公开(公告)号：US20140374689A1

    公开(公告)日：2014-12-25

    申请号：US13925951

    申请日：2013-06-25

    申请人： Elijah V. Karpov ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

    发明人： Elijah V. Karpov ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/146 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266

    摘要： Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory element includes a first conductive electrode. An insulating layer is disposed on the first conductive oxide and has an opening with sidewalls therein that exposes a portion of the first conductive electrode. A conductive oxide layer is disposed in the opening, on the first conductive electrode and along the sidewalls of the opening. A second electrode is disposed in the opening, on the conductive oxide layer.

    摘要翻译： 描述了导电氧化物随机存取存储器（CORAM）单元和制造CORAM单元的方法。 例如，用于存储元件的材料层堆叠包括第一导电电极。 绝缘层设置在第一导电氧化物上并且具有露出第一导电电极的一部分的侧壁的开口。 导电氧化物层设置在开口中，在第一导电电极上并且沿着开口的侧壁。 第二电极设置在开口中，在导电氧化物层上。

    Trigate static random-access memory with independent source and drain engineering, and devices made therefrom
    55.
    发明授权
    Trigate static random-access memory with independent source and drain engineering, and devices made therefrom 有权
    调整静态随机存取存储器，具有独立的源和漏极工程，以及由此制造的器件

    公开(公告)号：US08674448B2

    公开(公告)日：2014-03-18

    申请号：US13563432

    申请日：2012-07-31

    申请人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian S. Doyle ,  Robert S. Chau

    发明人： Ravi Pillarisetty ,  Willy Rachmady ,  Brian S. Doyle ,  Robert S. Chau

    IPC分类号： H01L21/70

    CPC分类号： H01L27/1104 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211

    摘要： A static random-access memory circuit includes at least one access device including source and drain sections for a pass region, at least one pull-up device and at least one pull-down device including source-and-drain sections for a pull-down region. The static random-access memory circuit is configured with external resistivity (Rext) for the pull-down region to be lower than Rext for the pass region. Processes of achieving the static random-access memory circuit include source-and-drain epitaxy.

    摘要翻译： 静态随机存取存储器电路包括至少一个访问装置，其包括用于通过区域的源极和漏极部分，至少一个上拉装置和至少一个下拉装置，其包括用于下拉的源极和漏极部分 地区。 静态随机存取存储器电路被配置为用于下拉区域的外部电阻率（Rext）低于用于通过区域的Rext。 实现静态随机存取存储器电路的过程包括源极和漏极外延。

    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
    56.
    发明授权
    Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication 有权
    非平面半导体器件部分或完全缠绕在栅极电极和制造方法

    公开(公告)号：US08273626B2

    公开(公告)日：2012-09-25

    申请号：US12893753

    申请日：2010-09-29

    申请人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    发明人： Scott A. Hareland ,  Robert S. Chau ,  Brian S. Doyle ,  Rafael Rios ,  Tom Linton ,  Suman Datta

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/66795

    摘要： A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

    摘要翻译： 描述了非平面半导体器件及其制造方法。 非平面半导体器件包括半导体本体，该半导体本体具有与形成在绝缘基板上方的底表面相对的顶表面，其中半导体本体具有一对横向相对的侧壁。 在半导体本体的横向相对的侧壁和半导体本体的底表面的至少一部分上的半导体本体的顶表面上形成栅极电介质。 栅极电极形成在半导体本体的顶表面上并与半导体本体的横向相对的侧壁上的栅电介质相邻并位于半导体本体的底表面上的栅电介质之下的栅电介质上。 在栅电极的相对侧的半导体本体中形成一对源/漏区。

    Capacitor, method of increasing a capacitance area of same, and system containing same
    58.
    发明授权
    Capacitor, method of increasing a capacitance area of same, and system containing same 有权
    电容器，增加电容面积相同的方法，以及包含其的系统

    公开(公告)号：US08138042B2

    公开(公告)日：2012-03-20

    申请号：US12967238

    申请日：2010-12-14

    申请人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

    发明人： Brian S. Doyle ,  Robert S. Chau ,  Suman Datta ,  Vivek De ,  Ali Keshavarzi ,  Dinesh Somasekhar

    IPC分类号： H01L27/108

    CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L29/785

    摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

    摘要翻译： 电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。 第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。 第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。 第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。 在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。