公开(公告)号：US20110193227A1

公开(公告)日：2011-08-11

申请号：US12729021

申请日：2010-03-22

申请人： Yao-Chun Chuang ,  Ching-Wen Hsiao ,  Chen-Cheng Kuo ,  Chen-Shien Chen

发明人： Yao-Chun Chuang ,  Ching-Wen Hsiao ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L23/31

CPC分类号： H01L23/49816 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01083 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00

摘要： Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %.

摘要翻译： 公开了使用无铅焊料在倒装芯片布置中提供坚固的焊接连接的装置和方法。 铜列从集成电路的输入/输出端子延伸。 包含镍，镍合金，钯，铂，钴，银，金及其合金的材料的盖层形成在铜柱的外表面上。 无铅焊料连接器设置在盖层上。 具有金属整理剂焊盘的基板与焊料连接器对准。 进行热回流。 金属表面可以是镍，镍合金和镍基材料。 在热回流之后，形成在铜端子柱和金属表面焊料焊盘之间的焊接连接小于0.5wt。 ％。

公开(公告)号：US08314482B2

公开(公告)日：2012-11-20

申请号：US11905869

申请日：2007-10-05

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

IPC分类号： H01L23/02

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/82

摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

摘要翻译： 本发明涉及一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。

公开(公告)号：US08587091B2

公开(公告)日：2013-11-19

申请号：US13533251

申请日：2012-06-26

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Chih-Ming Tzeng ,  Jyh-Rong Lin ,  Shan-Pu Yu

IPC分类号： H01L21/4763

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/351 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/82

摘要： A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.

摘要翻译： 一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。

公开(公告)号：US07888236B2

公开(公告)日：2011-02-15

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

公开(公告)号：US07632707B2

公开(公告)日：2009-12-15

申请号：US11269613

申请日：2005-11-09

申请人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

发明人： Shou-Lung Chen ,  Ching-Wen Hsiao ,  Yu-Hua Chen ,  Jeng-Dar Ko ,  Jyh-Rong Lin

IPC分类号： H01L21/00

CPC分类号： H01L24/97 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2224/82

摘要： The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

摘要翻译： 本发明公开了一种电子装置封装和封装方法。 具体地，公开了一种适用于具有增强的电气性能和散热效率的无扰动电子器件封装的封装的电子器件封装和方法。 该方法包括：提供具有多个通孔和多个电子器件的衬底; 在所述基板的表面上形成胶合层并将所述电子装置固定在所述胶合层上，其中所述电子装置具有分别与所述通孔对准的I / O单元; 在电子设备之间的间隙中形成多个固定层; 在固定层中分别与通孔对准的多个开口挖沟; 在通孔，开口和基板的表面的一部分上形成多个金属导电单元; 以及在所述衬底的另一表面上形成钝化层。

公开(公告)号：US07554639B2

公开(公告)日：2009-06-30

申请号：US11520679

申请日：2006-09-14

申请人： Ching-Wen Hsiao ,  Bang-Hao Wu ,  Hsin-Chun Chiang ,  Yu-Ming Chen

发明人： Ching-Wen Hsiao ,  Bang-Hao Wu ,  Hsin-Chun Chiang ,  Yu-Ming Chen

IPC分类号： G02F1/1337

CPC分类号： G02F1/13378 ,  G02F1/133784 ,  G02F1/1395 ,  G02F2001/133742 ,  G02F2001/133746

摘要： A method to control the pretilt angle of a liquid crystal device is disclosed. The claimed invention provides two substrates and at least one vertical alignment layers, which are fabricated on one side of each substrate and are opposite to each other. Moreover, a liquid crystal layer is sandwiched between the alignment layers, and the preferred embodiment of the liquid crystal device has an Optically Compensated Birefrigence (OCB) configuration. More particularly, before the process of alignment for the liquid crystal device is performed, a pretilt angle disclosed in the present invention is adjusted since at least one vertical alignment layer is treated with a particle beam generated by plasma or ions. The pretilt angle can range between 5 and 85 degrees.

摘要翻译： 公开了一种控制液晶装置预倾角的方法。 要求保护的发明提供了两个基板和至少一个垂直取向层，其被制造在每个基板的一侧上并且彼此相对。 此外，液晶层夹在取向层之间，液晶装置的优选实施例具有光学补偿双折射（OCB）构造。 更具体地说，在进行液晶装置的对准处理之前，调整本发明中公开的预倾角，因为至少一个垂直取向层用等离子体或离子产生的粒子束进行处理。 预倾角可以在5到85度之间。

公开(公告)号：US07411306B2

公开(公告)日：2008-08-12

申请号：US11194669

申请日：2005-08-02

申请人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

发明人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/15321 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

摘要翻译： 本发明涉及图像传感器模块的封装结构和方法。 该方法包括：提供具有第一图案化导电层的透明基板; 在所述透明基板上承载具有感光有源区域的图像传感器集成电路芯片和至少一个无源芯片，其中所述光敏有源区域面向所述透明基板; 在透明基板上形成绝缘堆积膜; 并且在绝缘堆积膜中形成多个导电通孔，其中导电通孔的端部与透明基板的无源芯片或第一图案化导电层连接，而导电通孔的另一端暴露在表面上 的绝缘堆积膜。 包装方法能够缩小图像传感器模块的结构，简化了处理步骤。

公开(公告)号：US20070263151A1

公开(公告)日：2007-11-15

申请号：US11520679

申请日：2006-09-14

申请人： Ching-Wen Hsiao ,  Bang-Hao Wu ,  Hsin-Chun Chiang ,  Yu-Ming Chen

发明人： Ching-Wen Hsiao ,  Bang-Hao Wu ,  Hsin-Chun Chiang ,  Yu-Ming Chen

IPC分类号： G02F1/1337

CPC分类号： G02F1/13378 ,  G02F1/133784 ,  G02F1/1395 ,  G02F2001/133742 ,  G02F2001/133746

摘要： A method to control the pretilt angle of a liquid crystal device is disclosed. The claimed invention provides two substrates and at least one vertical alignment layers, which are fabricated on one side of each substrate and are opposite to each other. Moreover, a liquid crystal layer is sandwiched between the alignment layers, and the preferred embodiment of the liquid crystal device has an Optically Compensated Birefrigence (OCB) configuration. More particularly, before the process of alignment for the liquid crystal device is performed, a pretilt angle disclosed in the present invention is adjusted since at least one vertical alignment layer is treated with a particle beam generated by plasma or ions. The pretilt angle can range between 5 and 85 degrees.

摘要翻译： 公开了一种控制液晶装置预倾角的方法。 要求保护的发明提供了两个基板和至少一个垂直取向层，其被制造在每个基板的一侧上并且彼此相对。 此外，液晶层夹在取向层之间，液晶装置的优选实施例具有光学补偿双折射（OCB）构造。 更具体地说，在进行液晶装置的对准处理之前，调整本发明中公开的预倾角，因为至少一个垂直取向层用等离子体或离子产生的粒子束进行处理。 预倾角可以在5到85度之间。

公开(公告)号：US20070002270A1

公开(公告)日：2007-01-04

申请号：US11242919

申请日：2005-10-05

申请人： Bang-Hao Wu ,  Ching-Wen Hsiao ,  Yu-Ming Chen ,  Hsin-Chun Chiang ,  Chung-Wen Wu

发明人： Bang-Hao Wu ,  Ching-Wen Hsiao ,  Yu-Ming Chen ,  Hsin-Chun Chiang ,  Chung-Wen Wu

IPC分类号： G02F1/1337

CPC分类号： G02F1/133788

摘要： A method that uses at least one hydrogen ion beam for alignment of liquid crystal molecules is proposed in the present invention. The method of the present invention is proposed to resolve the problems of physical destruction and surface deterioration of the alignment films caused by the conventional method using argon ions beams. The method of the present invention directly uses at least one hydrogen ion beam to impact the alignment film. Hence, the physical destruction of the alignment film is reduced. In addition, via the reaction between hydrogen ions and the alignment films, the quality of the alignment film is improved.

摘要翻译： 在本发明中提出了使用至少一个氢离子束来对准液晶分子的方法。 提出本发明的方法，以解决由使用氩离子束的常规方法引起的取向膜的物理破坏和表面劣化的问题。 本发明的方法直接使用至少一个氢离子束来冲击取向膜。 因此，取向膜的物理破坏减小。 此外，通过氢离子和取向膜之间的反应，取向膜的质量得到改善。

公开(公告)号：US20060030070A1

公开(公告)日：2006-02-09

申请号：US11194669

申请日：2005-08-02

申请人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

发明人： Fang-Jun Leu ,  Shou-Lung Chen ,  Ching-Wen Hsiao ,  Shan-Pu Yu ,  Jyh-Rong Lin ,  I-Hsuan Peng ,  Jian-Shu Wu ,  Hui-Mei Wu ,  Chien-Wei Chieh

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/07811 ,  H01L2924/15321 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.