Abstract:
Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.
Abstract:
A network device may pair with a particular satellite dish by storing a security key uniquely associated with the particular satellite dish. The network device may then receive encrypted data from the particular satellite dish, and decrypt the received encrypted data utilizing the security key. One or more circuits of the network device may be operable to prevent the network device from decrypting data from any satellite dish other than the particular satellite dish. The network device may be operable such that the security key is the only key that the network device can utilize for decrypting signals received via a particular interface and/or from a particular address. One or more circuits collocated with a satellite dish may be operable to encrypt data utilizing a security key stored in the one or more circuits. The security key may be unique to the one or more circuits and/or satellite dish.
Abstract:
A system may comprise a plurality of signal processing paths, a bin-wise combiner, an inverse transformation block, and a DAC. Each signal processing path may comprise a transformation block that is operable to transform a first time-domain digital signal to an associated frequency-domain signal having a plurality of subband signals. The bin-wise combiner may be operable to combine corresponding subband signals of the plurality of signal processing paths. The inverse transformation block may be operable to transform output of the bin-wise combiner to an second time-domain signal. The DAC may be operable to converts the second time-domain signal to a corresponding analog signal.
Abstract:
Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.
Abstract:
A receiver system and method for determining the location of a device in a wireless network having a plurality of transmitters is provided. The method includes receiving a signal at the device, transforming the received signal into a time-domain signal having a characteristic, and computing a range of the device from each of the plurality of transmitters based on the characteristic. Additionally, the method includes determining the location of the device based on the computed ranges. In certain embodiments, the characteristic may be a time of arrival, time difference of arrival, or a signal strength, and the wireless network is a DTV broadcasting network.
Abstract:
A radio integrated circuit includes, in part, an analog front end block, an analog-to-digital converter responsive to the analog-front end block, a digital signal processor responsive to the analog-to-digital converter and adapted to generate in-phase and quadrature signals, and a serial communication interface configured to receive and transmit the in-phase and quadrature signals. The serial communication interface supplies a gain control signal to the analog front end block when a switch disposed in the radio integrated circuit is in a first position. When the switch is in a second position, a gain control block disposed in the radio integrated circuit receives a gain control signal from the analog-to-digital converter and supplies the gain control signal to the analog front end block. The digital signal processor may be configured to interleave the in-phase and quadrature signals.
Abstract:
An Internet protocol low noise block downconverter (IP LNB) assembly, which is within a satellite dish assembly, may be operable to determine one or more baseline settings of the satellite dish assembly. The IP LNB assembly may monitor, periodically or aperiodically, one or more current settings that may correspond to the determined one or more baseline settings to identify deviations of the one or more current settings from the baseline settings. The results of the monitoring may be communicated to a satellite service provider. The satellite service provider may provide maintenance and/or service management for the satellite dish assembly based on the communicated results of the monitoring. The IP LNB assembly may determine a location setting via a GNSS module and determine an alignment setting via a directional sensor in the IP LNB assembly. The IP LNB assembly may determine a received signal strength based on a RSSI.
Abstract:
A network device (e.g., a cable modem) may support a normal mode of operation and a sleep mode of operation. While in the normal mode, a PHY of the network device may process a received signal to recover MPEG-TS packets, and convey the MPEG-TS packets to other components of the network device for further processing. While in the sleep mode, the PHY may process received MPEG-TS packets having a particular packet identifier and drop received MPEG-TS packets not having the particular packet identifier. The PHY may control transitions between the normal mode and the sleep mode in response to received signals having particular physical layer characteristics. The PHY may demodulate a received signal to recover an MPEG-TS packet; descramble portions of the MPEG-TS packet; inspect portions of the MPEG-TS packet; and control a mode of operation of the network device based on the contents of the MPEG transport stream.
Abstract:
A satellite reception assembly may comprise a memory collocated with a receive module and a basestation module. The receive module may receive a satellite signal and recover data carried in the satellite signal. The data may be stored in the memory. The stored data may be transmitted to mobile devices via the basestation module. Which portion of the recovered data is store in the memory may be based on demand for particular data in the coverage area served by the basestation module. Which portion of the recovered data is stored in the memory may be based on information provided by a satellite subscriber, such as the subscriber's anticipated location at one or more future time intervals.
Abstract:
Methods and systems for location determination and navigation using textual information may comprise capturing images of sources of textual information in the vicinity of a wireless communication device (WCD). Text may be extracted from the sources and a position of the WDC may be determined based on a comparison of the extracted text a stored database of textual information. An orientation of the text may be sensed and may be utilized with the extracted text and determined distances from the sources for the position determining. Locations of the sources and/or the captured images may be stored in the database. An instruction to capture images in a different orientation may be received when the positioning does not meet an accuracy requirement. A distance from the sources of textual information may be determined based on known optical properties of a camera in the WCD, such as focal length and/or and focus setting.