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公开(公告)号：US09069928B2
公开(公告)日：2015-06-30
申请号：US14175731
申请日：2014-02-07
Applicant: D-Wave Systems Inc.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H. S. Amin , Geordie Rose , David Grant , Miles F. H. Steininger , Paul I. Bunyk , Andrew J. Berkley
IPC: H03K19/195 , G06F15/76 , H03K3/38 , B82Y10/00 , G06N99/00
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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52.发明申请SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF A QUANTUM PROCESSOR BY REDUCING ERRORS 有权通过减少误差来提高量子处理器的性能的系统和方法公开(公告)号：US20150032994A1
公开(公告)日：2015-01-29
申请号：US14340303
申请日：2014-07-24
Applicant: D-WAVE SYSTEMS INC.
Inventor： Fabian Ariel Chudak , Christopher B. Rich , Paul I. Bunyk
CPC classification number: G06N99/002 , B82Y10/00
Abstract: Techniques for improving the performance of a quantum processor are described. Some techniques employ improving the processor topology through design and fabrication, reducing intrinsic/control errors, reducing thermally-assisted errors and methods of encoding problems in the quantum processor for error correction.
Abstract translation: 描述了用于改善量子处理器的性能的技术。 一些技术通过设计和制造来改进处理器拓扑，减少内在/控制误差，减少热辅助误差和量子处理器中编码问题的方法进行纠错。
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公开(公告)号：US20140246763A1
公开(公告)日：2014-09-04
申请号：US14109604
申请日：2013-12-17
Applicant: D-Wave Systems Inc.
Inventor： Paul I. Bunyk
CPC classification number: H01L27/18 , G01R31/2884 , G01R31/2891 , H01L24/05 , H01L24/13 , H01L24/81 , H01L39/045 , H01L39/24 , H01L2224/0401 , H01L2224/05008 , H01L2224/05023 , H01L2224/05179 , H01L2224/05548 , H01L2224/05568 , H01L2224/05573 , H01L2224/05611 , H01L2224/13007 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13163 , H01L2224/13176 , H01L2224/13183 , H01L2224/13562 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13611 , H01L2224/16238 , H01L2224/81191 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/15787 , H01L2924/35121 , H01L2924/00014 , H01L2924/014 , H01L2924/01076 , H01L2224/81 , H01L2924/00
Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.
Abstract translation: 描述了在超导芯片和超导芯片载体之间提供连续的，不间断的超导信号路径的超导互连结构。 超导互连结构采用超导焊料凸块和下凸块金属（“UBM”）的支柱。 超导互连结构用于两级焊料凸起工艺中，其中超导芯片首先结合到测试模块进行筛选，然后结合到芯片封装模块进行操作。 测试模块或芯片封装模块或两者都可以包括用于同时承载多个超导芯片的多芯片模块。
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公开(公告)号：US20130313526A1
公开(公告)日：2013-11-28
申请号：US13958339
申请日：2013-08-02
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
CPC classification number: H01L39/223 , B82Y10/00 , G06N99/002 , H01L27/18
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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公开(公告)号：US20230297869A1
公开(公告)日：2023-09-21
申请号：US18003563
申请日：2021-06-29
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , Reza Molavi , Kelly T.R. Boothby , Mark H. Volkmann
CPC classification number: G06N10/40 , H10N60/805
Abstract: A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.
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Patent Agency Ranking
公开(公告)号：US11507871B2
公开(公告)日：2022-11-22
申请号：US16307382
申请日：2017-06-07
Applicant: D-WAVE SYSTEMS INC.
Inventor： Kelly T. R. Boothby , Paul I. Bunyk
Abstract: Topologies for analog computing systems may include cells of qubits which may implement a tripartite graph and cross substantially orthogonally. Qubits may have an H-shape or an l-shape, qubits may change direction within a cell. Topologies may be comprised of two or more different sub-topologies. Qubits may be communicatively coupled to non-adjacent cells by long-range couplers. Long-range couplers may change direction within a cell. A cell may have two or more different type of long-range couplers. A cell may have shifted qubits, more than one type of inter-cell couplers, more than one type of intra-cell couplers and long-range couplers.
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公开(公告)号：US20220020913A1
公开(公告)日：2022-01-20
申请号：US17330037
申请日：2021-05-25
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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58.发明申请公开(公告)号：US20220019929A1
公开(公告)日：2022-01-20
申请号：US17387654
申请日：2021-07-28
Applicant: D-WAVE SYSTEMS INC.
Inventor： Paul I. Bunyk , James King , Murray C. Thom , Mohammad H. Amin , Anatoly Smirnov , Sheir Yarkoni , Trevor M. Lanting , Andrew D. King , Kelly T. R. Boothby
Abstract: The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
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公开(公告)号：US20210384406A1
公开(公告)日：2021-12-09
申请号：US17321819
申请日：2021-05-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Shuiyuan Huang , Byong H. Oh , Douglas P. Stadtler , Edward G. Sterpka , Paul I. Bunyk , Jed D. Whittaker , Fabio Altomare , Richard G. Harris , Colin C. Enderud , Loren J. Swenson , Nicolas C. Ladizinsky , Jason J. Yao , Eric G. Ladizinsky
IPC: H01L39/24 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/18 , H01L39/12
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
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公开(公告)号：US20210342289A1
公开(公告)日：2021-11-04
申请号：US17355458
申请日：2021-06-23
Applicant: D-WAVE SYSTEMS INC.
Inventor： Alexander Maassen van den Brink , Peter Love , Mohammad H.S. Amin , Geordie Rose , David Grant , Miles F.H. Steininger , Paul I. Bunyk , Andrew J. Berkley
Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
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