公开(公告)号：US20130005096A1

公开(公告)日：2013-01-03

申请号：US13368584

申请日：2012-02-08

申请人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

发明人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

公开(公告)号：US09972716B2

公开(公告)日：2018-05-15

申请号：US14826439

申请日：2015-08-14

申请人： Jin-Bum Kim ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Su-Jin Jung ,  Bon-Young Koo

发明人： Jin-Bum Kim ,  Seok-Hoon Kim ,  Chul Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Su-Jin Jung ,  Bon-Young Koo

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/32 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/3221 ,  H01L29/165 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/785

摘要： Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

公开(公告)号：US09595611B2

公开(公告)日：2017-03-14

申请号：US14262712

申请日：2014-04-26

申请人： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

发明人： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

摘要： A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

摘要翻译： 半导体器件可以包括在衬底上并排形成的第一和第二鳍片，形成在第一鳍片上并具有杂质的第一掺杂浓度的第一升高掺杂区域，形成在第二鳍片上的第二高掺杂区域， 将第一升高掺杂区域和第二升高掺杂区域彼此连接的桥。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20120184079A1

公开(公告)日：2012-07-19

申请号：US13428900

申请日：2012-03-23

申请人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/28273 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

摘要翻译： 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US20120091469A1

公开(公告)日：2012-04-19

申请号：US13271615

申请日：2011-10-12

申请人： Keum-Seok Park ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Hong-Bum Park

发明人： Keum-Seok Park ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Hong-Bum Park

IPC分类号： H01L29/772

CPC分类号： H01L29/66621 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.

摘要翻译： 提供了半导体器件，其包括具有从第一表面的相对侧凹入的第一表面和第二表面的衬底，形成在第一表面上并具有栅极绝缘层和栅电极的栅极图案，碳掺杂硅缓冲层 形成在第二表面上，以及掺杂有n型掺杂剂或p型掺杂剂的源极和漏极区，其外延生长在硅缓冲层上以从栅极绝缘层的顶表面升高。

公开(公告)号：US08853010B2

公开(公告)日：2014-10-07

申请号：US13368584

申请日：2012-02-08

申请人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

发明人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L21/339 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

摘要翻译： 半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。 沟道区位于衬底上并位于第一和第二应力产生外延区之间。 栅电极在沟道区上。 沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

公开(公告)号：US08716093B2

公开(公告)日：2014-05-06

申请号：US13428900

申请日：2012-03-23

申请人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

发明人： Jin-Bum Kim ,  Kwan-Heum Lee ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sun-Ghil Lee

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823425 ,  H01L21/28273 ,  H01L21/823418 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

摘要： A semiconductor device can include a first gate electrode including a gate insulating pattern, a gate conductive pattern and a capping pattern that are sequentially stacked on a semiconductor substrate, and a first spacer of a low dielectric constant disposed on a lower sidewall of the first gate electrode. A second spacer of a high dielectric constant, that is greater than the low dielectric constant, is disposed on an upper sidewall of the first gate electrode above the first spacer.

摘要翻译： 半导体器件可以包括第一栅电极，其包括依次层叠在半导体衬底上的栅极绝缘图案，栅极导电图案和覆盖图案，以及布置在第一栅极的下侧壁上的低介电常数的第一间隔物 电极。 高介电常数的第二间隔物大于低介电常数，设置在第一间隔物上方的第一栅电极的上侧壁上。

公开(公告)号：US08664633B2

公开(公告)日：2014-03-04

申请号：US13220777

申请日：2011-08-30

申请人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

发明人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

IPC分类号： H01L29/06

CPC分类号： H01L27/1021 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

摘要翻译： 非易失性存储器件可以包括衬底上的第一字线，第一字线上的绝缘层和绝缘层上的第二字线，使得绝缘层在第一和第二字线之间。 位柱可以在相对于衬底的表面垂直的方向上相邻于第一字线，绝缘层和第二字线延伸，并且位柱可以是导电的。 此外，第一存储单元可以包括电耦合在第一字线和位柱之间的第一电阻可变元件，并且第二存储单元可以包括电耦合在第二字线和位柱之间的第二电阻可变元件。 还讨论了相关方法和系统。

公开(公告)号：US09368495B2

公开(公告)日：2016-06-14

申请号：US14576368

申请日：2014-12-19

申请人： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

发明人： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC分类号： H01L21/00 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

摘要： A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

摘要翻译： 半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层， 多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

公开(公告)号：US09190410B2

公开(公告)日：2015-11-17

申请号：US14466078

申请日：2014-08-22

申请人： Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

发明人： Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/02

CPC分类号： H01L27/0922 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7843

摘要： A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.

摘要翻译： 一种制造半导体器件的方法包括分别在第一和第二区域的衬底上形成第一和第二栅极结构，通过第一高密度等离子体工艺在衬底上形成第一覆盖层，使得第一覆盖层覆盖第一 以及除了其侧壁之外的第二栅极结构，去除第一区域中的第一覆盖层的一部分，使用第一栅极结构去除第一区域中的衬底的上部，以形成第一沟槽，并形成 第一外延层，以填充第一沟槽。