公开(公告)号：US06628563B1

公开(公告)日：2003-09-30

申请号：US10191228

申请日：2002-07-09

申请人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

发明人： Fu-Chang Hsu ,  Peter W. Lee ,  Hsing-Ya Tsao

IPC分类号： G11C800

CPC分类号： G11C16/08 ,  G11C2216/22

摘要： A non-volatile integrated circuit memory having an AND-like array structure that is capable of simultaneous reading and writing of digital data to multiple memory cells within the integrated circuit memory has memory cells within an array block of memory cells are arranged in columns and rows. A plurality of block bit lines is in communication with each array block of memory cells such that each block bit line interconnects the memory cells of one column of memory cells within one array block. A plurality of word lines is in communication with each array block of memory cells such that each word line interconnects the memory cells of one row within one array block. The integrated circuit memory further includes a plurality of global bit lines in communication with the array blocks to select a column of the array blocks and to transfer the digital data from and to the array blocks. A bit line selector selectively connects the plurality of global bit lines to the block bit lines. An array controller controls selection of a row of a block of the array, control transfer of the digital data from selected global bit lines to selected block bit lines, control transfer of the digital data to other selected global bit lines from other selected bit lines to allow simultaneous transfer of the digital data from and to selected memory cells.

摘要翻译： 具有AND状阵列结构的非易失性集成电路存储器能够同时读取和写入数字数据到集成电路存储器内的多个存储器单元，存储单元阵列块内的存储单元被排列成列和行 。 多个块位线与存储器单元的每个阵列块通信，使得每个块位线互连一个阵列块内的一列存储器单元的存储单元。 多个字线与存储器单元的每个阵列块通信，使得每个字线互连一个阵列块内的一行的存储单元。 集成电路存储器还包括与阵列块通信的多个全局位线，以选择阵列块的列并将数字数据从阵列块传送到阵列块。 位线选择器有选择地将多个全局位线连接到块位线。 阵列控制器控制对阵列的一行的选择，控制数字数据从所选择的全局位线传送到选择的块位线，控制数字数据从其它所选位线到其它所选择的全局位线的传送 允许从选定的存储器单元同时传送数字数据。

公开(公告)号：US06515910B1

公开(公告)日：2003-02-04

申请号：US10076826

申请日：2002-02-15

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Tam Tran ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Tam Tran ,  Fu-Chang Hsu

IPC分类号： G11C1606

CPC分类号： G11C16/3409 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

摘要： A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.

摘要翻译： 实现了对存储器阵列器件中的存储器单元的擦除条件进行测试的方法。 该方法进一步扩展到在擦除和擦除条件下检测和校正的方法。 存储器阵列器件的一部分的擦除条件被改变以形成擦除部分和非擦除部分。 未擦除部分中的存储器单元的控制栅极被迫到足以关闭已擦除单元的正常截止状态电压。 被擦除部分的未选择子部分中的存储器单元的控制栅极被强制为保证的关断状态电压，其将关闭包括那些被擦除的单元的擦除的单元。 被擦除部分的选定子部分中的存储器单元的控制栅极被强制为检查电压。 此后，测量擦除部分的所选子部分的位线电流，以确定擦除部分的所选子部分的擦除条件。

公开(公告)号：US06498752B1

公开(公告)日：2002-12-24

申请号：US09940159

申请日：2001-08-27

申请人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

发明人： Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

IPC分类号： G11C1606

CPC分类号： G11C16/3445 ,  G11C16/16 ,  G11C16/3459

摘要： The present invention discloses a novel method for erasing an ETOX type and an AND type NOR flash memory arrays. The operations of the methods includes block erase which increases the Vt of the memory cell, block erase verify to check if the Vt of the erased cell is greater than a predetermined voltage Vtoff, page reverse program which reduces the Vt of the memory cell below a predetermine voltage Vtmax, reverse program verify which checks that the Vt of the memory cell is below Vtmax, page correction which corrects the Vt of cells on a page basis to be above a predetermined voltage Vtmin, and correction verify which checks that the Vt of the memory cells is above Vtmin. According to the present invention, the erase operation is performed to increase the Vt of erased cells by applying the positive high voltages to the selected word lines with bit lines and source lines grounded. The reverse program operation is performed to decrease the Vt of erased cells by applying the negative high voltage to the selected word lines with the source lines and bit lines grounded. For the ETOX cell an FN tunneling scheme is utilized for the Erase operation and CHE for the correction operation. The AND cell uses FN tunneling for both erase and correction operations.

摘要翻译： 本发明公开了一种用于擦除ETOX型和AND型NOR闪存阵列的新方法。 方法的操作包括增加存储器单元的Vt的块擦除，块擦除验证以检查擦除单元的Vt是否大于预定电压Vtoff，页面反向程序，其将存储器单元的Vt减小到低于 预先确定电压Vtmax，反向程序验证哪个检查存储器单元的Vt低于Vtmax，将页面上的单元格的Vt校正为高于预定电压Vtmin的页面校正，以及校正验证哪个检查Vt 存储单元高于Vtmin。 根据本发明，执行擦除操作以通过将位线和源极线接地的正高电压施加到所选择的字线来增加擦除单元的Vt。 执行反向编程操作以通过将源极线和位线接地来对所选择的字线施加负高电压来减小擦除单元的Vt。 对于ETOX单元，使用FN隧道方案进行擦除操作和CHE进行校正操作。 AND单元使用FN隧道进行擦除和校正操作。

公开(公告)号：US06275417B1

公开(公告)日：2001-08-14

申请号：US09680651

申请日：2000-10-06

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao

IPC分类号： G11C1604

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C11/5621 ,  G11C16/26 ,  G11C2211/5634

摘要： Data stored in multi-level memory cells is rapidly read out with high resolution by generating and coupling a predetermined and preferably low number of large magnitude jump-like voltage changes to the control gates of the memory cells. The magnitude of the jumps can be a substantial fraction of the power supply level and will be many times the &Dgr;Vt levels associated with the memory cells, e.g., the control gate voltage changes in jump-steps from say 4 V to 6 V to 8 V. Use of a low number of jump-steps (e.g., two or three) reduces read out time by permitting read out of a plurality of Vt levels during a given control voltage magnitude. Further, use of large but different magnitude control gate voltages provides good read out resolution over the range of Vt values. Reference cells are provided to improve tracking, and DRAM-type sense amplifiers are provided to maintain high noise immunity.

摘要翻译： 存储在多电平存储单元中的数据通过产生并将预定的和优选的低数量的大幅度的类似跳变的电压变化耦合到存储器单元的控制栅极而以高分辨率快速读出。 跳跃的幅度可以是电源电平的很大一部分，并且将是与存储器单元相关联的DELTAVt电平的许多倍，例如，控制栅极电压在从4V变为6V至8V的跳变步长 使用低数量的跳跃步骤（例如，两个或三个）通过允许在给定的控制电压幅度期间读出多个Vt电平来减少读出时间。 此外，使用大但不同幅度的栅极电压在Vt值的范围内提供良好的读出分辨率。 提供参考单元以改善跟踪，并且提供DRAM型读出放大器以保持高抗噪声性。

公开(公告)号：US5848000A

公开(公告)日：1998-12-08

申请号：US819323

申请日：1997-03-18

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/10 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3431 ,  G11C8/10 ,  G11C8/12 ,  H01L27/115 ,  G11C16/24 ,  G11C2211/5642 ,  G11C2216/20 ,  G11C7/18 ,  G11C8/00

摘要： A flash memory address decoder includes a plurality of voltage terminals to receive a plurality of voltages, an address terminal to receive a plurality of address signals and a procedure terminal to receive a procedure signal. A block decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a block select signal. A wordline decoder is coupled to the address terminal and configured to decode a portion of the address signals to provide a wordline select signal. A wordline selector circuit is coupled to the block decoder and the wordline decoder and configured to receive the block select signal and the wordline select signal and to activate addressed wordlines, where the wordline selector is configured to selectively activate addressed wordlines in the flash transistor array and to provide at least two different operational voltages simultaneously on different wordlines in the flash transistor array to accomplish a predetermined procedure responsive to the procedure signal. In one embodiment, a the address decoder includes a latch structure that latches addressed wordlines and provides operational voltages to the wordlines. In another embodiment, the block decoder and wordline decoder include latch structures that latch the block select signal and the wordline select signal to provide operational voltages to the wordline selector. Advantages of the invention include high accuracy and flexibility to read, erase and program the flash memory.

摘要翻译： 闪存地址解码器包括多个用于接收多个电压的电压端子，用于接收多个地址信号的地址端子和用于接收过程信号的过程终端。 块解码器耦合到地址终端并且被配置为对部分地址信号进行解码以提供块选择信号。 字线解码器耦合到地址终端，并且被配置为对地址信号的一部分进行解码以提供字线选择信号。 字线选择器电路耦合到块解码器和字线解码器并且被配置为接收块选择信号和字线选择信号并激活寻址字线，其中字线选择器被配置为选择性地激活闪存晶体管阵列中的寻址字线， 以在闪光晶体管阵列中的不同字线上同时提供至少两个不同的操作电压，以响应于过程信号来完成预定的过程。 在一个实施例中，地址解码器包括锁存寻址字线并向字线提供工作电压的锁存结构。 在另一个实施例中，块解码器和字线解码器包括锁存块选择信号和字线选择信号以向字线选择器提供工作电压的锁存结构。 本发明的优点包括读取，擦除和编程闪存的高精度和灵活性。

公开(公告)号：US5822252A

公开(公告)日：1998-10-13

申请号：US676066

申请日：1996-07-05

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/00

CPC分类号： G11C16/3413 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C8/08 ,  G11C8/10 ,  H01L27/115 ,  G11C16/24 ,  G11C2211/5642 ,  G11C2211/5644 ,  G11C2216/20 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14

摘要： The invention provides a flash memory and decoder with overerase repair that can provide three word line voltages to overcome the overerased problems. The wordline decoder includes a wordline latch that provides a high flexibility of erasing size so that single/multiple sub-wordlines, single/multiple wordlines, single/multiple block, and whole array can be erased simultaneously. An exemplary embodiment of a flash memory wordline decoder that can provide three voltages includes a plurality of voltage terminals to receive a plurality of voltages, a plurality of address terminals to receive a plurality of address signals, a procedure terminal to receive a procedure signal, and a plurality of output wordlines adapted to be coupled to a bank of flash transistors. The wordline decoder circuit is configured to decode the address signals and includes a plurality of latches coupled to the wordlines and configured to latch the wordlines and to provide one of a plurality of operational voltages on the wordlines to accomplish a predetermined operation responsive to the procedure signal. The plurality of voltage terminals are configured in a way that the high voltage required for erasure or for programming needs not be discharged in verification. Another exemplary embodiment provides a wordline decoder that provides three wordline voltages for verification and repairing, and also for erasure. Advantages of the invention include available full verifications for erasure, repairing and programming, tight cell threshold distribution, high efficiency repairing, no discharging the high voltage cells in verifications, full range verification voltages.

摘要翻译： 本发明提供了具有过度修复的闪存和解码器，其可以提供三个字线电压以克服过度存在的问题。 字线解码器包括字线锁存器，其提供擦除大小的高灵活性，使得可以同时擦除单个/多个子字线，单个/多个字线，单个/多个块和整个阵列。 可以提供三个电压的闪存字线解码器的示例性实施例包括多个用于接收多个电压的电压端子，多个地址端子以接收多个地址信号，接收过程信号的过程终端，以及 适于耦合到一组闪存晶体管的多个输出字线。 字线解码器电路被配置为对地址信号进行解码，并且包括耦合到字线的多个锁存器，并被配置为锁存字线并且在字线上提供多个工作电压中的一个，以响应于过程信号来完成预定的操作 。 多个电压端子被配置为在验证中不需要消除擦除或编程所需的高电压。 另一示例性实施例提供一种字线解码器，其提供用于验证和修复的三个字线电压，并且还用于擦除。 本发明的优点包括用于擦除，修复和编程的可用的完整验证，紧密的单元阈值分布，高效率修复，在验证中不排放高电压单元，全范围验证电压。

公开(公告)号：USRE37419E1

公开(公告)日：2001-10-23

申请号：US09430060

申请日：1999-10-29

申请人： Fu-Change Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

发明人： Fu-Change Hsu ,  Hsing-Ya Tsao ,  Peter W. Lee

IPC分类号： G11C1604

CPC分类号： G11C11/5621 ,  G11C8/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C16/3445 ,  G11C2211/5621 ,  H01L27/115

摘要： A flash memory circuit includes a word line decoder with even and odd word line latches and a source line decoder with a source line latch. The word line decoders and the source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and a verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that may be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments and having segmented source lines controlled by source segment control lines and transistors, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing. Several different approaches are presented for the layout of source segment control lines and transistors as well as the word lines.

摘要翻译： 闪存电路包括具有偶数和奇数字线锁存器的字线解码器和具有源极线锁存器的源极线解码器。 字线解码器和源极线解码器提供同时擦除闪存中的两个相邻字线的存储单元的能力，并且逐字地验证存储单元字。 通过同时擦除两个相邻行，本发明的实施例消除了与常规闪存电路相关的过度擦除和源干扰问题。 解码架构提供了可能从一对到大量多对字线的灵活的擦除大小。 通过将字线的存储单元划分成多个段并具有由源段控制线和晶体管控制的分段源极线，解码电路还提供选择用于擦除的字线段的存储单元的能力。 对于源段控制线和晶体管以及字线的布局提出了几种不同的方法。

公开(公告)号：US08996785B2

公开(公告)日：2015-03-31

申请号：US12807997

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/00 ,  G11C16/32 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0408

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US20110072201A1

公开(公告)日：2011-03-24

申请号：US12807997

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/02 ,  G11C16/06

CPC分类号： G11C16/32 ,  G11C16/0408

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US06687154B2

公开(公告)日：2004-02-03

申请号：US10364033

申请日：2003-02-11

申请人： Peter W. Lee ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Fu-Chang Hsu

IPC分类号： G11C1604

CPC分类号： H01L27/1126 ,  G11C11/005 ,  G11C16/0433 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115

摘要： A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.

摘要翻译： 实现了存储单元装置。 存储单元器件包括具有栅极，漏极和源极的第一晶体管。 第二个晶体管具有栅极，漏极和源极。 第一晶体管漏极耦合到阵列位线。 第二晶体管源耦合到阵列源极线。 第一晶体管源耦合到第二晶体管漏极。 第一晶体管和第二晶体管包括一个闪存晶体管和一个掩模ROM晶体管。 可以读取掩模ROM晶体管的编程状态。