公开(公告)号：US09406803B2

公开(公告)日：2016-08-02

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L21/326 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

公开(公告)号：US20160163831A1

公开(公告)日：2016-06-09

申请号：US14676909

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7854

Abstract: A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.

Abstract translation: 一种方法包括在半导体衬底上形成翅片。 在翅片附近形成隔离结构。 在隔离结构上方延伸的翅片的一部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片部分并且限定将翅片与基底分离的第一绝缘层。

公开(公告)号：US09349730B2

公开(公告)日：2016-05-24

申请号：US13945415

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Ajey Poovannummoottil Jacob ,  Kangguo Cheng ,  Bruce B. Doris ,  Nicolas Loubet ,  Prasanna Khare ,  Ramachandra Divakaruni

IPC: H01L21/20 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US20160093739A1

公开(公告)日：2016-03-31

申请号：US14963683

申请日：2015-12-09

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: A FinFET device includes a fin structure positioned in the channel region of the device and a gate structure positioned above the fin structure, wherein the fin structure includes a portion of a semiconductor substrate and an epi semiconductor material positioned vertically above the portion of the semiconductor substrate. Sidewall spacers are positioned adjacent the gate structure and a fin cavity is positioned in source/drain regions of the device, wherein the fin structure has edges in a gate width direction that are substantially self-aligned with the sidewall spacers and the semiconductor substrate defines the bottom of the fin cavity. A silicon etch stop layer is positioned on and in contact with the edges of the fin structure and within the fin cavity, and a stressed semiconductor material is positioned on and in contact with the silicon etch stop layer and at least partially within the fin cavity.

Abstract translation: FinFET器件包括位于器件的沟道区域中的鳍结构和位于鳍结构上方的栅极结构，其中鳍结构包括半导体衬底的一部分和位于半导体衬底的部分上方的外延半导体材料 。 侧壁间隔件位于栅极结构附近并且翅片空腔位于器件的源极/漏极区域中，其中鳍状结构具有栅极宽度方向上的边缘，其基本上与侧壁间隔物自对准，并且半导体衬底限定 翅片底部底部。 硅蚀刻停止层定位在翅片结构的边缘并且在翅片空腔内并与其接触，并且应力半导体材料定位在硅蚀刻停止层上并且与硅蚀刻停止层接触并且至少部分地位于翅片腔内。

公开(公告)号：US20160013291A1

公开(公告)日：2016-01-14

申请号：US14859729

申请日：2015-09-21

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/161 ,  H01L21/31

CPC classification number: H01L29/6681 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A fin structure is formed in and above a substrate and includes a portion of a substrate semiconductor material, a first epi semiconductor material formed above the substrate semiconductor material portion, and a second epi semiconductor material formed above the first epi semiconductor material. A sacrificial gate structure is formed above the fin structure, a sidewall spacer is formed adjacent the sacrificial gate structure, and at least one etching process is performed to remove portions of the fin structure positioned laterally outside of the sidewall spacer so as to define a fin cavity source/drain regions and to expose edges of the fin structure positioned under the spacer. An epi etch stop layer is formed on the exposed edges of the fin structure and within the fin cavity, and the first epi semiconductor material is removed selectively from the fin structure so as to form a channel cavity therein.

Abstract translation: 鳍状结构形成在基板的上方，上方形成有基板半导体材料的一部分，形成在基板半导体材料部分的上方的第一外延半导体材料，以及形成在第一外延半导体材料的上方的第二外延半导体材料。 牺牲栅极结构形成在翅片结构的上方，邻近牺牲栅极结构形成侧壁间隔物，并且执行至少一个蚀刻工艺以去除位于侧壁间隔物外侧的翅片结构的部分，从而限定翅片 空腔源极/漏极区域并且暴露位于间隔物下方的鳍结构的边缘。 在翅片结构的暴露边缘和翅片腔内形成外延蚀刻停止层，并且第一外延半导体材料被选择性地从翅片结构移除，以在其中形成沟槽。

公开(公告)号：US09236479B2

公开(公告)日：2016-01-12

申请号：US14708405

申请日：2015-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/78603

Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.

公开(公告)号：US09224865B2

公开(公告)日：2015-12-29

申请号：US13945627

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

Abstract translation: FinFET具有包括半导体衬底，半导体鳍片和横跨翅片的栅极的结构。 翅片各自具有连接到基底的底部区域和顶部活动区域。 位于底部和顶部翅片区域之间的是中间堆叠，位于垂直细长的源和垂直细长的排水管之间。 堆叠包括顶部通道区域和紧邻通道区域下方的电介质区域，提供通道的电隔离。 部分隔离结构可以与栅极第一和栅极末端制造工艺一起使用。

公开(公告)号：US09147748B1

公开(公告)日：2015-09-29

申请号：US14267555

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Andreas Knorr ,  Christopher Prindle

IPC: H01L21/283 ,  H01L29/66 ,  H01L21/311 ,  H01L21/285 ,  H01L29/45 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41758 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42372 ,  H01L29/45 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract translation: 本文公开的一种示例性方法包括去除侧壁间隔件和栅极盖层，从而暴露牺牲栅极结构的上表面和侧壁，在器件的源极/漏极区域上方以及在侧壁和上部上形成蚀刻停止层 牺牲栅极结构的表面，在蚀刻停止层上方形成第一绝缘材料层，去除牺牲栅极结构，以便限定由蚀刻停止层的部分横向限定的替代栅极腔，形成替代栅极结构 并且在替换栅极结构上方形成第二栅极盖层。

公开(公告)号：US20150137237A1

公开(公告)日：2015-05-21

申请号：US14086199

申请日：2013-11-21

Applicant: Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat K. Akarvardar

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/761 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/0646 ,  H01L29/66795

Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (FinFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an undoped epitaxial (epi) layer between the embedded S/D and the gate structure. The device may further include an epitaxial (epi) bottom region of the embedded S/D, wherein the epi bottom region is counter doped to a polarity of the embedded S/D, and a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions is doped and the epi bottom region is undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

Abstract translation: 提供了用于隔离集成电路（IC）器件（例如，鳍式场效应晶体管（FinFET））中的源极和漏极区域的方法。 具体地，FinFET器件包括形成在鳍式衬底上的栅极结构; 栅极结构的有源鳍式沟道下方的隔离氧化物; 形成在栅极结构和隔离氧化物附近的嵌入式源极和漏极（S / D）; 以及嵌入式S / D和栅极结构之间的未掺杂的外延（epi）层。 该器件可以进一步包括嵌入式S / D的外延（epi）底部区域，其中外延底部区域被反掺杂到嵌入式S / D的极性，以及一组注入在epi底部区域下方的注入区域， 其中所述一组注入区域是掺杂的，并且所述外延底部区域是未掺杂的。 在一种方法中，嵌入式S / D包括用于p沟道金属氧化物半导体场效应晶体管（PMOSFET）的P ++掺杂硅锗（SiGe）和用于n沟道金属氧化物半导体场效应晶体管的N ++氮化硅（SiN） 半导体场效应晶体管（NMOSFET）。

公开(公告)号：US09023705B1

公开(公告)日：2015-05-05

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8232 ,  H01L29/423 ,  H01L27/088 ,  H01L27/105 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。