公开(公告)号：US09184162B2

公开(公告)日：2015-11-10

申请号：US14615762

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Xiuyu Cai ,  Ajey Poovannummoottil Jacob

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/76208 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0653

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract translation: 提供了Fin场效应晶体管集成电路及其制造方法。 翅片场效应晶体管集成电路包括从半导体衬底延伸的多个鳍。 多个翅片中的每一个包括翅片侧壁，并且多个翅片中的每一个延伸到翅片高度，使得具有槽底部的凹槽限定在相邻翅片之间。 第二电介质位于槽内，其中第二电介质在槽底部直接接触半导体衬底。 第二电介质延伸到小于翅片高度的第二介电高度，使得突出的翅片部分在第二电介质上方延伸。 第一电介质位于翅片侧壁和第二电介质之间。

公开(公告)号：US09117875B2

公开(公告)日：2015-08-25

申请号：US14155499

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。

公开(公告)号：US20150200128A1

公开(公告)日：2015-07-16

申请号：US14155499

申请日：2014-01-15

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/762 ,  H01L21/324 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。

公开(公告)号：US20150137308A1

公开(公告)日：2015-05-21

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

公开(公告)号：US20150123166A1

公开(公告)日：2015-05-07

申请号：US14069955

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Michael Hargrove ,  Ruilong Xie

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

Abstract: are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract translation: 是涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 本文公开的方法和装置包括形成掺杂的硅衬底鳍片，然后在衬底鳍片周围形成硅/锗层。 所述方法和装置还包括使用栅极第一或栅极末端技术在硅/锗层周围形成栅极结构。

公开(公告)号：US20180096998A1

公开(公告)日：2018-04-05

申请号：US15689711

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Murat Kerem Akarvardar

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649

Abstract: Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric layer is formed that encapsulates a plurality of fins. A second dielectric layer is formed that surrounds the first dielectric layer and the plurality of fins. A surface of the second dielectric layer relative to a surface of the first dielectric layer. A liner is conformally deposited on the surface of the first dielectric layer and on the recessed surface of the second dielectric layer. A section of the liner is removed to expose the surface of the first dielectric layer. The exposed surface of the first dielectric layer is recessed to reveal a portion of each of the plurality of fins.

公开(公告)号：US09882052B2

公开(公告)日：2018-01-30

申请号：US15197892

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Judson Holt ,  Jinping Liu ,  Jody Fronheiser ,  Bharat Krishnan ,  Churamani Gaire ,  Timothy James McArdle ,  Murat Kerem Akarvardar

IPC: H01L21/335 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.

公开(公告)号：US09679972B1

公开(公告)日：2017-06-13

申请号：US15133683

申请日：2016-04-20

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Jody Fronheiser ,  Murat Kerem Akarvardar ,  Stephen Bedell ,  Joel Kanyandekwe

IPC: H01L29/775 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/78 ,  H01L29/7849

Abstract: A semiconductor structure can include a substrate and a substrate layer. The substrate can be formed of silicon and the substrate layer can be formed of silicon germanium. Above the substrate and under the substrate layer there can be provided a multilayer substructure. The multilayer substructure can include a first layer and a second layer. The first layer can be formed of a first material and the second layer can be formed of second material. A method can include forming a multilayer substructure on a substrate, annealing the multilayer substructure, and forming a substrate layer on the multilayer substructure.

公开(公告)号：US20170133406A1

公开(公告)日：2017-05-11

申请号：US14934042

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02598 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor structure, comprising a semiconductor substrate and at least one fin coupled to the semiconductor substrate, wherein the fin comprises at least two active regions and at least one insulator region, wherein all active regions and all insulator regions are stacked and each insulator region is disposed between two active regions. Methods, apparatus, and systems for forming such a semiconductor structure.

公开(公告)号：US09530869B2

公开(公告)日：2016-12-27

申请号：US14643409

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Steven Bentley

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract translation: 本文公开的一种说明性方法包括在器件的源极/漏极区域中形成绝缘材料层，其中绝缘材料层具有与栅极盖层的上表面基本上平面的上表面 使绝缘材料层凹陷，使得其凹陷的上表面暴露在鳍片的表面上，执行另一蚀刻工艺以移除鳍片的至少一部分，从而限定位于凹鳍片上方的凹陷散热片沟槽，并形成外延 所述半导体材料至少部分地位于所述凹陷散热片沟槽中。