公开(公告)号：US20160343659A1

公开(公告)日：2016-11-24

申请号：US14718502

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L23/525 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L23/5256 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.

Abstract translation: 提供一种形成包括熔丝的半导体器件的方法，包括：提供绝缘层上的绝缘体上半导体结构（SOI）结构和形成在绝缘层上的半导体层，在与中心相邻的半导体层上形成凸起的半导体区域 并且对半导体层的中心部分和凸起的半导体区域进行硅化处理，以形成硅化半导体层和硅化凸起的半导体区域。

公开(公告)号：US09466685B2

公开(公告)日：2016-10-11

申请号：US14628947

申请日：2015-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/49 ,  H01L27/092 ,  H01L23/535 ,  H01L21/8238

CPC classification number: H01L23/535 ,  H01L21/823842 ,  H01L23/485 ,  H01L27/092 ,  H01L29/4966

Abstract: A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

Abstract translation: 半导体结构包括衬底，设置在衬底上的至少一个导电柱和设置在衬底上的导电结构。 导电柱包括内部和外层，其设置在内部的下方并且在内部的侧面。 导电结构还包括内部部分和外层，其设置在内部部分的下方并且在内部部分的外侧。 导电结构环形地包围至少一个导电柱中的每一个。 所述至少一个导电柱中的每一个的外层与导电结构的外层接触。 至少一个导电柱的外层和导电结构的外层由不同的金属材料形成。

公开(公告)号：US09443871B2

公开(公告)日：2016-09-13

申请号：US14592069

申请日：2015-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/321 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L29/417 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract translation: 一种形成半导体器件结构的方法包括：提供具有绝缘体上半导体（SOI）结构的衬底，所述SOI衬底包括形成在半导体本体衬底上的掩埋氧化物（BOX）层上形成的半导体层，形成 描绘SOI衬底内的第一区域和第二区域的沟槽隔离结构，去除第一区域中的半导体层和BOX层，用于在第一区域内暴露半导体本体衬底，形成具有电极的第一半导体器件 在所述第一区域中暴露的半导体体基板，在所述第二区域中形成第二半导体器件，所述第二半导体器件包括设置在所述半导体层上的栅极结构和所述第二区域中的BOX层，以及执行用于定义 电极和栅极结构基本上延伸的公共高度电平。

公开(公告)号：US20160260606A1

公开(公告)日：2016-09-08

申请号：US14635071

申请日：2015-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L21/033 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/665

Abstract: The present disclosure provides methods of forming a masking pattern and a semiconductor device structure, wherein printed half pitches of, for example, about 20 nm or less may be formed. A method of forming a masking pattern is provided wherein an unpatterned mask layer is formed over a semiconductor device structure provided in and on an upper surface of a semiconductor substrate, and the unpatterned mask layer is patterned for forming the masking pattern over the semiconductor device structure. The unpatterned mask layer is patterned by forming a dummy pattern having at least one recess on the unpatterned mask layer, forming a first sidewall spacer structure adjacent to sidewalls of the recess, removing the dummy pattern, forming a second sidewall spacer structure on the first sidewall spacer structure, removing the first sidewall spacer structure, and etching the unpatterned mask layer in alignment with the second sidewall spacer structure.

Abstract translation: 本公开提供了形成掩模图案和半导体器件结构的方法，其中可以形成例如约20nm或更小的印刷半间距。 提供一种形成掩模图案的方法，其中在半导体衬底的上表面上设置半导体器件结构上形成未图案化的掩模层，并且对未图案化的掩模层进行图案化以在半导体器件结构上形成掩模图案 。 通过在未图案化的掩模层上形成具有至少一个凹部的虚设图案来形成未图案化的掩模层，形成与凹部的侧壁相邻的第一侧壁间隔结构，去除虚拟图案，在第一侧壁上形成第二侧壁间隔结构 间隔结构，去除第一侧壁间隔结构，以及蚀刻与第二侧壁间隔结构对准的未图案化掩模层。

公开(公告)号：US20160204219A1

公开(公告)日：2016-07-14

申请号：US15076850

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Till Schloesser ,  Peter Baars

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L21/823462 ,  H01L27/11509 ,  H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k dielectric layer, the first high-k dielectric layer having a first thickness and comprising hafnium. The second circuit element comprises a second electrode structure that includes a second high-k dielectric layer having a ferroelectric behavior, wherein the second high-k dielectric layer has a second thickness and comprises hafnium, and wherein the second thickness is greater than the first thickness.

Abstract translation: 半导体器件包括第一和第二电路元件。 第一电路元件包括包括第一高k电介质层的第一电极结构，第一高k电介质层具有第一厚度并且包含铪。 第二电路元件包括第二电极结构，其包括具有铁电性能的第二高k电介质层，其中第二高k电介质层具有第二厚度并且包括铪，并且其中第二厚度大于第一厚度 。

公开(公告)号：US09337045B2

公开(公告)日：2016-05-10

申请号：US14458718

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Carsten Grass ,  Peter Baars

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/28194 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure provides a method of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element is formed on the basis of a replacement gate process replacing a dummy gate structure of a semiconductor device of the semiconductor circuit element by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a high-k material that is in the ferroelectric phase. In some illustrative embodiments herein, a semiconductor device is provided, the semiconductor device having a gate structure disposed over an active region of a semiconductor substrate. Herein, the gate structure comprises a spacer structure and a dummy gate structure which is replaced by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a ferroelectric high-k material.

Abstract translation: 本公开提供了一种形成半导体电路元件和半导体电路元件的方法，其中，基于替换栅极工艺形成半导体电路元件，替代栅极工艺通过栅极替代半导体电路元件的半导体器件的伪栅极结构 氧化物结构和栅电极材料，其中栅极氧化物结构包括处于铁电相中的高k材料。 在本文的一些说明性实施例中，提供半导体器件，该半导体器件具有设置在半导体衬底的有源区上方的栅极结构。 这里，栅极结构包括由栅极氧化物结构和栅电极材料代替的间隔结构和虚拟栅极结构，其中栅极氧化物结构包括铁电高k材料。

公开(公告)号：US09324854B2

公开(公告)日：2016-04-26

申请号：US14226176

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Till Schloesser ,  Peter Baars ,  Frank Jakubowski

IPC: H01L29/772 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L21/285 ,  H01L21/288 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.

Abstract translation: 半导体器件包括位于有源区上方的高k金属栅电极结构，具有位于栅极高度的顶表面，并且包括高k电介质材料和电极金属。 引出的漏极和源极区域横向邻近高k金属栅极电极结构定位并连接到有源区域，并且每个升高的漏极和源极区域的顶表面位于栅极下方的接触高度水平处 身高。 蚀刻停止层位于凸起的漏极和源极区域的顶表面上方，并且接触元件连接到凸起的漏极和源极区域之一，接触元件延伸穿过蚀刻停止层， k金属栅极电极结构和升高的漏极和源极区域。

公开(公告)号：US09214463B2

公开(公告)日：2015-12-15

申请号：US14326623

申请日：2014-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/76889 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/4232 ,  H01L29/4975 ,  H01L29/78

Abstract: An integrated circuit device includes a PMOS transistor and an NMOS transistor. The PMO transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the PMOS transistor, and a multi-part second sidewall spacer positioned adjacent the first sidewall spacer of the PMOS transistor, wherein the multi-part second sidewall spacer includes an upper spacer and a lower spacer. The NMOS transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the NMOS transistor, and a single second sidewall spacer positioned adjacent the first sidewall spacer of the NMOS transistor. A metal silicide region is positioned on each of the gate electrodes and on each of the at least one source/drain regions of the PMOS and the NMOS transistors.

Abstract translation: 集成电路器件包括PMOS晶体管和NMOS晶体管。 PMO晶体管包括栅极电极，至少一个源极/漏极区域，邻近PMOS晶体管的栅电极定位的第一侧壁间隔物和邻近PMOS晶体管的第一侧壁间隔物定位的多部分第二侧壁间隔物，其中 多部分第二侧壁间隔件包括上间隔件和下间隔件。 NMOS晶体管包括栅极电极，至少一个源极/漏极区域，邻近NMOS晶体管的栅电极定位的第一侧壁间隔件和邻近NMOS晶体管的第一侧壁间隔物定位的单个第二侧壁间隔物。 金属硅化物区域位于PMOS和NMOS晶体管的每个栅极电极和至少一个源极/漏极区域中的每一个上。

公开(公告)号：US20130126980A1

公开(公告)日：2013-05-23

申请号：US13718158

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures.

Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和导电触点的各种方法以及包括该栅极结构和导电触点的装置。 一个示例性器件包括位于半导体衬底上方的多个栅极结构，位于栅极结构的相应侧壁附近的至少一个侧壁隔离物，以及在半导体衬底的源极/漏极区域中的金属硅化物区域，金属硅化物区域延伸 横向地接触定位在每个栅极结构附近的侧壁间隔件。 此外，该装置还包括位于多个栅极结构之间的导电触点，导电触点具有导电接触金属硅化物区域的下部分和位于下部部分上方的上部，其中下部分 横向宽于上部并且横向延伸，以便接近靠近每个门结构的侧壁间隔件。

公开(公告)号：US10475901B1

公开(公告)日：2019-11-12

申请号：US15956926

申请日：2018-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/266 ,  H01L27/11 ,  H01L21/3105 ,  H01L29/786 ,  H01L29/08 ,  H01L21/762

Abstract: The present disclosure relates to manufacturing techniques and respective semiconductor devices in which the capping material of gate electrode structures may be removed together with portions of the capping material of resistors on the basis of a highly controllable directional etch process, wherein raised drain and source regions may be protected on the basis of a fill material.