公开(公告)号：US20120241090A1

公开(公告)日：2012-09-27

申请号：US13429638

申请日：2012-03-26

申请人： Jun Yoshikawa ,  Naoki Matsumoto ,  Naoki Mihara ,  Wataru Yoshikawa ,  Shota Yoshimura ,  Kazuki Takahashi

发明人： Jun Yoshikawa ,  Naoki Matsumoto ,  Naoki Mihara ,  Wataru Yoshikawa ,  Shota Yoshimura ,  Kazuki Takahashi

IPC分类号： B05C9/00 ,  H01L21/3065

CPC分类号： H01J37/32192 ,  H01J37/3244 ,  H01J37/32651

摘要： A plasma processing apparatus includes a processing chamber; a gas supply unit for supplying a processing gas into the processing chamber; a microwave generator for generating microwave; an antenna for introducing the microwave for plasma excitation into the processing chamber; a coaxial waveguide provided between the microwave generator and the antenna; a holding unit, disposed to face the antenna in a direction of a central axis line of the coaxial waveguide, for holding a processing target substrate; a dielectric window, provided between the antenna and the holding unit, for transmitting the microwave from the antenna into the processing chamber; and a dielectric rod provided in a region between the holding unit and the dielectric window along the central axis line.

摘要翻译： 等离子体处理装置包括处理室; 气体供给单元，用于将处理气体供给到所述处理室中; 用于产生微波的微波发生器; 用于将用于等离子体激发的微波引入处理室的天线; 设置在微波发生器和天线之间的同轴波导; 保持单元，设置成在所述同轴波导的中心轴线方向上面对所述天线，用于保持处理对象基板; 设置在所述天线和所述保持单元之间的用于将所述微波从所述天线发射到所述处理室中的电介质窗口; 以及设置在沿着中心轴线的保持单元和电介质窗口之间的区域中的介电棒。

公开(公告)号：US20120203010A1

公开(公告)日：2012-08-09

申请号：US13502834

申请日：2010-10-20

申请人： Naoki Matsumoto ,  Takanori Miyazaki ,  Shinichi Ishikawa

发明人： Naoki Matsumoto ,  Takanori Miyazaki ,  Shinichi Ishikawa

IPC分类号： C07D209/82

CPC分类号： C09K11/06 ,  C07D209/88 ,  C07D401/04 ,  C09K2211/1029 ,  H01L51/0072 ,  H01L51/5016 ,  H01L51/5056 ,  H01L51/5064 ,  H05B33/14

摘要： A carbazole compound represented by the following formula: wherein, when m=1, n=0, Ar1, Ar2, Ar3 and X2 are C6-50 aryl or C4-50 heteroaryl, provided that Ar1 and Ar2, or Ar3 and X2 may form together a ring; X1═C6-50 arylene; R1, R2, R4, R5 and R7 are H, halogen, amino, C1-18 alkyl, C1-18 alkoxy, C6-50 aryl or C4-50 heteroaryl, R3 and R6 are H, halogen, C1-18 alkyl, C1-18 alkoxy, C6-50 aryl or C4-50 heteroaryl; when m=0, n=1-3, Ar3, Ar4 and Ar5 are C6-50 aryl or C4-50 heteroaryl, Ar4 and Ar5 may form together a ring; X1═C1-18 alkyl, C6-50 aryl or C4-50 heteroaryl; X2═C6-50 arylene; R1-R7 are H, halogen, C1-18 alkyl, C1-18 alkoxy, C6-50 aryl or C4-50 heteroaryl; when m=0, n=0, X1═C1-18 alkyl, C6-50 aryl or C4-50 heteroaryl; Ar3 and X2 are C6-50 aryl or C4-50 heteroaryl; R2═H, halogen, C1-18 alkyl, C1-18 alkoxy; R1 and R3-R7 are H, halogen, C1-18 alkyl, C1-18 alkoxy, C6-50 aryl or C4-50 heteroaryl. The carbazole compound is suitable for an organic EL device.

摘要翻译： 由下式表示的咔唑化合物：其中当m = 1时n = 0，Ar 1，Ar 2，Ar 3和X 2为C 6-50芳基或C 4-50杂芳基，条件是Ar 1和Ar 2或Ar 3和X 2可以形成 一起一个戒指 X1 = C6-50亚芳基; R1，R2，R4，R5和R7是H，卤素，氨基，C1-18烷基，C1-18烷氧基，C6-50芳基或C4-50杂芳基，R3和R6是H，卤素，C1-18烷基，C1 -18烷氧基，C6-50芳基或C4-50杂芳基; 当m = 0时，n = 1-3，Ar 3，Ar 4和Ar 5为C 6-50芳基或C 4-50杂芳基，Ar 4和Ar 5可以一起形成环; X1 = C1-18烷基，C6-50芳基或C4-50杂芳基; X2 = C6-50亚芳基; R 1 -R 7是H，卤素，C 1-18烷基，C 1-18烷氧基，C 6-50芳基或C 4-50杂芳基; 当m = 0时，n = 0，X1 = C1-18烷基，C6-50芳基或C4-50杂芳基; Ar 3和X 2是C 6-50芳基或C 4-50杂芳基; R 2 = H，卤素，C 1-18烷基，C 1-18烷氧基; R1和R3-R7是H，卤素，C1-18烷基，C1-18烷氧基，C6-50芳基或C4-50杂芳基。 咔唑化合物适用于有机EL器件。

公开(公告)号：US20120129419A1

公开(公告)日：2012-05-24

申请号：US13378057

申请日：2010-03-01

申请人： Naoki Yoshimoto ,  Naoki Matsumoto ,  Shota Ueki ,  Hidenobu Nakanishi ,  Yasuhiro Ueda

发明人： Naoki Yoshimoto ,  Naoki Matsumoto ,  Shota Ueki ,  Hidenobu Nakanishi ,  Yasuhiro Ueda

IPC分类号： H01J9/20 ,  G09G5/02

CPC分类号： G02F1/136259 ,  G02F2001/136254 ,  G02F2001/136272

摘要： After source lines have been grouped into a plurality of blocks including adjacent ones of the source lines, in a region outside a display region, at least one inspection bus line for inputting an inspection signal to pixels is formed in association with each of the blocks, and the source lines in each of the blocks are connected to the associated inspection bus line, thereby forming an inspection circuit including the inspection bus lines. Then, an inspection signal is supplied to the pixels from the inspection bus line through the source lines in each of the blocks in the inspection circuit, and a target pixel is compared with a plurality of comparative pixels arranged along one of the source lines along which the target pixel is located, with a gray-level display provided on the display region, thereby detecting a presence of a black point defect in the target pixel.

摘要翻译： 在源极线已经被分组为包括相邻源极线的多个块之后，在显示区域外的区域中，与每个块相关联地形成用于向像素输入检查信号的至少一个检查总线， 并且每个块中的源极线连接到相关联的检查总线，从而形成包括检查总线线路的检查电路。 然后，检查信号通过检查电路中的每个块中的源极线从检查总线提供给像素，并且将目标像素与沿其中一条源极线布置的多个比较像素进行比较 目标像素位于显示区域上的灰度级显示，从而检测目标像素中是否存在黑点缺陷。

公开(公告)号：US20110272097A1

公开(公告)日：2011-11-10

申请号：US13186145

申请日：2011-07-19

申请人： Akira Koshiishi ,  Masaru Sugimoto ,  Kunihiko Hinata ,  Noriyuki Kobayashi ,  Chishio Koshimizu ,  Ryuji Ohtani ,  Kazuo Kibi ,  Masashi Saito ,  Naoki Matsumoto ,  Yoshinobu Ooya ,  Manabu Iwata ,  Daisuke Yano ,  Yohei Yamazawa ,  Hidetoshi Hanaoka ,  Toshihiro Hayami ,  Hiroki Yamazaki ,  Manabu Sato

发明人： Akira Koshiishi ,  Masaru Sugimoto ,  Kunihiko Hinata ,  Noriyuki Kobayashi ,  Chishio Koshimizu ,  Ryuji Ohtani ,  Kazuo Kibi ,  Masashi Saito ,  Naoki Matsumoto ,  Yoshinobu Ooya ,  Manabu Iwata ,  Daisuke Yano ,  Yohei Yamazawa ,  Hidetoshi Hanaoka ,  Toshihiro Hayami ,  Hiroki Yamazaki ,  Manabu Sato

IPC分类号： C23F1/08

CPC分类号： H01J37/32422 ,  H01J37/32018 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32522 ,  H01J37/32834 ,  H01J2237/2001 ,  H01J2237/334 ,  H01J2237/3344 ,  H01L21/67069 ,  Y10S156/915

摘要： A plasma etching apparatus includes an upper electrode and a lower electrode, between which plasma of a process gas is generated to perform plasma etching on a wafer W. The apparatus further comprises a cooling ring disposed around the wafer, a correction ring disposed around the cooling ring, and a variable DC power supply directly connected to the correction ring, the DC voltage being preset to provide the correction ring with a negative bias, relative to ground potential, for attracting ions in the plasma and to increase temperature of the correction ring to compensate for a decrease in temperature of a space near the edge of the target substrate due to the cooling ring.

摘要翻译： 等离子体蚀刻装置包括上电极和下电极，在其间产生处理气体的等离子体以在晶片W上进行等离子体蚀刻。该装置还包括设置在晶片周围的冷却环，设置在冷却周围的校正环 环和直接连接到校正环的可变直流电源，所述直流电压被预设为向校正环提供相对于地电位的负偏压，用于吸引等离子体中的离子并将校正环的温度增加到 补偿由于冷却环导致的目标基板的边缘附近的空间的温度的降低。

公开(公告)号：US20110163323A1

公开(公告)日：2011-07-07

申请号：US13045886

申请日：2011-03-11

申请人： Kensaku Motoki ,  Takuji Okahisa ,  Naoki Matsumoto

发明人： Kensaku Motoki ,  Takuji Okahisa ,  Naoki Matsumoto

IPC分类号： H01L29/20

CPC分类号： C30B25/00 ,  C30B25/02 ,  C30B29/406 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L33/007

摘要： The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.

摘要翻译： 制造GaN单晶衬底的方法包括掩模层形成步骤，在GaAs衬底2上形成具有彼此分离设置的多个开口窗口10的掩模层8; 以及在掩模层8上生长由GaN制成的外延层12的外延层生长步骤。

公开(公告)号：US07960284B2

公开(公告)日：2011-06-14

申请号：US12018198

申请日：2008-01-23

申请人： Akihiro Hachigo ,  Naoki Matsumoto ,  Takayuki Nishiura

发明人： Akihiro Hachigo ,  Naoki Matsumoto ,  Takayuki Nishiura

IPC分类号： H01L21/302

CPC分类号： H01L21/02052 ,  C30B29/40 ,  C30B33/12 ,  H01L21/02019 ,  H01L21/02024 ,  H01L21/30621

摘要： Affords a III-V compound semiconductor substrate manufacturing method that enables enhancement of the substrate PL intensity. In such a III-V compound semiconductor substrate manufacturing method, first, the surface 3a of a wafer 3 is polished (polishing step). Second, the surface 3a of the wafer 3 is cleaned (first cleaning step S7). Next, the surface 3a of the wafer 3 is subjected to first dry-etching, employing a halogen-containing gas, while first bias voltage is applied to a chuck 24 for carrying the wafer 3. Subsequently, the surface 3a of the wafer 3 is subjected to second dry-etching, employing the halogen-containing gas (second dry-etching step S11), while second bias power lower than the first bias power is applied to the chuck 24.

摘要翻译： 提供能够提高基板PL强度的III-V族化合物半导体基板的制造方法。 在这种III-V族化合物半导体衬底的制造方法中，首先对晶片3的表面3a进行研磨（研磨工序）。 其次，清洁晶片3的表面3a（第一清洗步骤S7）。 接下来，对用于承载晶片3的卡盘24施加第一偏置电压，对晶片3的表面3a进行第一次干蚀刻，然后使用含卤素气体。随后，晶片3的表面3a 使用含卤素气体（第二干法蚀刻步骤S11）进行第二干蚀刻，同时将低于第一偏压功率的第二偏压功率施加到卡盘24。

公开(公告)号：US20110126765A1

公开(公告)日：2011-06-02

申请号：US12951380

申请日：2010-11-22

申请人： Yohei Yamazawa ,  Naoki Matsumoto ,  Masahide Iwasaki ,  Naohiko Okunishi

发明人： Yohei Yamazawa ,  Naoki Matsumoto ,  Masahide Iwasaki ,  Naohiko Okunishi

IPC分类号： C23C16/513

CPC分类号： H01J37/32174 ,  H01J37/32091 ,  H01J37/32522 ,  H05H1/46

摘要： A parallel resonance frequency can be adjusted in order to stably and securely block different high frequency noises flowing into a line such as a power feed line or a signal line from electric members including a high frequency electrode within a processing chamber. A filter 102(1) coaxially accommodates a coil 104(1) within a cylindrical outer conductor 110, and a ring member 122 is coaxially installed between the coil 104(1) and the outer conductor 110. The ring-shaped member 122 may be a plate body of a circular ring shape on a plane orthogonal to an axial direction of the outer conductor 110 and made of a conductor such as cupper or aluminum and electrically connected with the outer conductor 110 while electrically insulated from the coil 104(1).

摘要翻译： 可以调节并联谐振频率，以便稳定且可靠地阻止流入来自包括处理室内的高频电极的电气部件的馈电线或信号线的线路的不同高频噪声。 过滤器102（1）在圆柱形外导体110内同轴地容纳线圈104（1），并且环形构件122同轴地安装在线圈104（1）和外导体110之间。环形构件122可以是 在与外导体110的轴向正交的平面上并且由诸如铜或铝的导体制成并且与外导体110电连接并且与线圈104（1）电绝缘的平板体。

公开(公告)号：US20110068434A1

公开(公告)日：2011-03-24

申请号：US12833145

申请日：2010-07-09

申请人： Sayuri Yamaguchi ,  Naoki Matsumoto ,  Hidenori Mikami

发明人： Sayuri Yamaguchi ,  Naoki Matsumoto ,  Hidenori Mikami

IPC分类号： H01L29/205 ,  H01L21/20 ,  B26D1/00

CPC分类号： H01L21/02021 ,  C30B29/406 ,  C30B33/00 ,  Y10T83/04

摘要： A nitride semiconductor substrate having a main surface serving as a semipolar plane and provided with a chamfered portion capable of effectively preventing cracking and chipping, a semiconductor device fabricated using the nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate and the semiconductor device are provided. The nitride semiconductor substrate includes a main surface inclined at an angle of 71° or more and 79° or less with respect to the (0001) plane toward the [1-100] direction or inclined at an angle of 71° or more and 79° or less with respect to the (000-1) plane toward the [−1100] direction; and a chamfered portion located at an edge of an outer periphery of the main surface. The chamfered portion is inclined at an angle θ1 or θ2 of 5° or more and 45° or less with respect to adjacent one of the main surface and a backside surface on a side opposite to the main surface. Accordingly, cracking and chipping occurring from the edge of the outer periphery of the nitride semiconductor substrate can be effectively suppressed.

摘要翻译： 一种氮化物半导体衬底，其主表面用作半极性平面，并且具有能够有效防止裂纹和碎裂的倒角部分，使用氮化物半导体衬底制造的半导体器件，以及用于制造氮化物半导体衬底和半导体器件的方法 被提供。 氮化物半导体衬底包括相对于（0001）面朝向[1-100]方向以71°以上且79°以下的角度倾斜的主面或倾斜71°以上79°的主表面 °或更小，相对于（000-1）面朝向[-1100]方向; 以及位于主表面的外周边缘的倒角部分。 倒角部分相对于主表面的相邻一侧和与主表面相对的一侧的后侧表面以角度θ1或θ2倾斜5°以上且45°以下。 因此，可以有效地抑制从氮化物半导体基板的外周边缘发生的裂纹和切屑。

公开(公告)号：US20110049679A1

公开(公告)日：2011-03-03

申请号：US12940733

申请日：2010-11-05

申请人： Keiji ISHIBASHI ,  Hidenori Mikami ,  Naoki Matsumoto

发明人： Keiji ISHIBASHI ,  Hidenori Mikami ,  Naoki Matsumoto

IPC分类号： H01L29/04 ,  H01L21/78

CPC分类号： H01L21/02021 ,  C30B29/403 ,  C30B33/00 ,  H01L24/32 ,  H01L33/0075 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/12042 ,  Y10S438/928 ,  Y10S438/959 ,  Y10S438/977 ,  H01L2924/00014 ,  H01L2924/00

摘要： A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 μm-10 μm thick edge process-induced degradation layer.

摘要翻译： 氮化物半导体晶片通过研磨晶片的底面进行平面加工，例如通过KOH去除底部工艺诱导的降解层，蚀刻底面，通过与100重量％-60重量％粘合的橡胶砂轮倒角， ＃3000-＃600金刚石颗粒和0重量％-40重量％的氧化物颗粒，研磨和抛光晶片的顶表面，蚀刻顶表面以消除顶部工艺诱导的降解层并保持0.5μm-10μm厚 边缘过程诱导的降解层。

公开(公告)号：US20110039417A1

公开(公告)日：2011-02-17

申请号：US12866545

申请日：2009-02-06

申请人： Naoki Matsumoto ,  Kazuyuki Kato ,  Masafumi Shikata ,  Masaru Sasaki

发明人： Naoki Matsumoto ,  Kazuyuki Kato ,  Masafumi Shikata ,  Masaru Sasaki

IPC分类号： H01L21/465 ,  H01L21/46

CPC分类号： H05H1/46 ,  H01J37/32192 ,  H01J37/32238

摘要： A dielectric board (20) is arranged on a ceiling surface, which is of a processing container (2) and faces a susceptor (3), a slot antenna (30) having a plurality of slots (33) which pass through microwaves is arranged on an upper surface of the dielectric board (20), and a protruding member (21), which is composed of a member different from the dielectric board (20) and eliminates abnormal discharge, is provided on a lower peripheral section of the dielectric board (20). A field strength at the peripheral section of the dielectric board (20) is controlled by adjusting a space between an outer circumference surface (22) of a cylindrical section of the protruding member (21) and a side wall inner circumference surface (5a) of the processing container (2) or adjusting the thickness of the cylindrical section of the protruding member (21).

摘要翻译： 在处理容器（2）的顶棚面上配置有面向基座（3）的电介质板（20），具有通过微波的多个槽（33）的缝隙天线（30） 在所述电介质基板（20）的上表面上设置有与所述电介质板（20）不同的部件构成并且消除异常放电的突出部件（21） （20）。 通过调整突出构件（21）的圆筒部的外周面（22）与侧壁内周面（5a）之间的空间来控制电介质基板（20）的周边部的场强， 处理容器（2）或调整突出部件（21）的圆筒部的厚度。