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63 条记录 (耗时 0.025 秒)

    Image sensors and methods of operating the same
    51.
    发明申请
    Image sensors and methods of operating the same 有权
    图像传感器及其操作方法

    公开(公告)号：US20110108704A1

    公开(公告)日：2011-05-12

    申请号：US12805723

    申请日：2010-08-17

    申请人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

    发明人： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

    IPC分类号： H01L27/146 ,  H01L31/09 ,  H01L31/101 ,  H01L31/102

    CPC分类号： H04N9/045 ,  H01L27/14643 ,  H04N5/3745

    摘要： Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

    摘要翻译： 图像传感器及其操作方法。 图像传感器包括包括多个像素的像素阵列。 多个像素中的每一个包括光电传感器，其电压 - 电流特性根据入射光的能量而变化，并且产生由入射光的能量确定的感测电流; 根据用于复位所述多个像素中的至少一个的复位信号，被激活以产生参考电流的复位单元; 以及转换单元，其将感测电流和参考电流分别转换为感测电压和参考电压。

    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices
    52.
    发明申请
    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 失效
    磁性分组存储器存储设备，包括这种设备的存储器系统以及控制这些设备的方法

    公开(公告)号：US20100208381A1

    公开(公告)日：2010-08-19

    申请号：US12658807

    申请日：2010-02-16

    申请人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    IPC分类号： G11B19/02

    CPC分类号： G11C11/15 ,  G11C5/04

    摘要： A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.

    摘要翻译： 存储器件由将磁信息存储在磁结构的多个域中的磁结构构成。 写单元响应于控制信号向磁结构施加写入电流，将信息写入磁结构的多个域中的至少一个。 读取单元通过响应于控制信号向磁性结构施加读取电流，从磁性结构的多个域中的至少一个域读取信息。 畴壁移动控制单元耦合到磁结构的一部分，并且响应于控制信号将存储在磁结构中的多个域中的信息移动到磁结构中的其他区域。 写单元，读单元和域壁移动控制单元都耦合到提供控制信号的相同控制信号线。

    Oscillator reducing clock signal variations due to variations in voltage or temperature
    53.
    发明授权
    Oscillator reducing clock signal variations due to variations in voltage or temperature 有权
    振荡器减少由于电压或温度变化引起的时钟信号变化

    公开(公告)号：US07538619B2

    公开(公告)日：2009-05-26

    申请号：US11790012

    申请日：2007-04-23

    申请人： Ho-jung Kim

    发明人： Ho-jung Kim

    IPC分类号： H03L7/085

    CPC分类号： H03L1/00 ,  H03K3/011 ,  H03K3/354

    摘要： Provided is an oscillator including a logic signal generator and a clock generator. The logic signal generator generates a first logic signal and a second logic signal that have the same period but have different logic level transition timing. The clock generator generates a clock signal in response to the first logic signal and the second logic signal. The oscillator compensates for an amount of variation of a reference current using a compensation current, thereby maintaining a constant period of the clock signal.

    摘要翻译： 提供了包括逻辑信号发生器和时钟发生器的振荡器。 逻辑信号发生器产生具有相同周期但具有不同逻辑电平转换时序的第一逻辑信号和第二逻辑信号。 时钟发生器响应于第一逻辑信号和第二逻辑信号产生时钟信号。 振荡器使用补偿电流来补偿参考电流的变化量，从而保持时钟信号的恒定周期。

    Driving circuits, power devices and electronic devices including the same
    55.
    发明授权
    Driving circuits, power devices and electronic devices including the same 有权
    驱动电路，功率器件和包括它们的电子器件

    公开(公告)号：US08803565B2

    公开(公告)日：2014-08-12

    申请号：US13064264

    申请日：2011-03-15

    申请人： Ho-jung Kim ,  Jae-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang ,  Ki-ha Hong

    发明人： Ho-jung Kim ,  Jae-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang ,  Ki-ha Hong

    IPC分类号： H03K17/16

    CPC分类号： H03K17/163 ,  H03K17/284

    摘要： A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

    摘要翻译： 功率器件包括具有控制端子和输出端子的开关器件; 以及驱动电路，被配置为向控制端子提供驱动电压，使得控制端子和输出端子之间的电压保持小于或等于临界电压。 根据开关装置的电流 - 电压特性来确定驱动电压达到目标电平所需的上升时间。 而且，当控制端子与输出端子之间的电压超过临界电压时，控制端子与输出端子之间产生漏电流。

    Non-volatile memory device and method of manufacturing the same
    56.
    发明授权
    Non-volatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08357992B2

    公开(公告)日：2013-01-22

    申请号：US12659516

    申请日：2010-03-11

    申请人： Ho-jung Kim ,  In-kyeong Yoo ,  Chang-jung Kim ,  Ki-ha Hong

    发明人： Ho-jung Kim ,  In-kyeong Yoo ,  Chang-jung Kim ,  Ki-ha Hong

    IPC分类号： H01L23/52 ,  H01L29/00

    CPC分类号： H01L27/222 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/73 ,  G11C2213/79 ,  H01L27/24

    摘要： The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines.

    摘要翻译： 非易失性存储器件可以包括衬底，在垂直方向上的衬底上的多个第一信号线，具有连接到多个第一信号线的端部的多个存储器单元，垂直于第一信号线的多个第二信号线 基板上的多个第一信号线，并且各自连接到多个存储单元的另一端，以及多个选择元件，并且连接到多个第一信号线中的至少两个。

    Information storage devices including vertical nano wires
    58.
    发明授权
    Information storage devices including vertical nano wires 失效
    信息存储设备包括垂直纳米线

    公开(公告)号：US08089797B2

    公开(公告)日：2012-01-03

    申请号：US12659515

    申请日：2010-03-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Sun-ae Seo ,  Sung-chul Lee

    IPC分类号： G11C19/00

    CPC分类号： G11C19/0808 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires.

    摘要翻译： 存储单元包括：存储单元阵列单元，具有垂直地布置在基板上的多个纳米线，所述多个纳米线中的每一个具有用于存储信息的多个域; 形成在所述基板上并被配置为选择所述多个纳米线中的至少一个的纳米线选择单元; 域移动控制单元，形成在所述基板上，并且被配置为控制相对于所述多个纳米线中的至少一个的域移动操作; 以及读/写控制单元，形成在所述基板上并被配置为控制关于所述多根纳米线中的至少一个的读取操作和写入操作中的至少一个。

    Driving circuits, power devices and electric devices including the same
    59.
    发明申请
    Driving circuits, power devices and electric devices including the same 有权
    驱动电路，功率器件和包括其的电子器件

    公开(公告)号：US20110273116A1

    公开(公告)日：2011-11-10

    申请号：US12929779

    申请日：2011-02-15

    申请人： Ho-jung Kim

    发明人： Ho-jung Kim

    IPC分类号： H02K7/14 ,  G05F1/00 ,  H03K3/00

    CPC分类号： H03K17/166 ,  H03K17/08122 ,  H03K17/0822 ,  H03K17/167 ,  H03K2217/0063 ,  H03K2217/0081

    摘要： A power device includes a switching device and a control unit. The switching device has a control terminal and an output terminal. The control unit is configured to control a rising time required for a driving voltage for controlling the switching device to reach a target level such that a voltage between the control terminal and the output terminal is maintained less than or equal to a critical voltage. When the voltage between the control terminal and the output terminal is greater than the critical voltage, leakage current is generated between the control terminal and the output terminal.

    摘要翻译： 功率器件包括开关器件和控制单元。 开关装置具有控制端子和输出端子。 控制单元被配置为控制用于控制开关器件达到目标电平的驱动电压所需的上升时间，使得控制端子和输出端子之间的电压保持小于或等于临界电压。 当控制端子与输出端子之间的电压大于临界电压时，控制端子与输出端子之间产生漏电流。

    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit
    60.
    发明申请
    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit 有权
    非易失性逻辑电路，包括非易失性逻辑电路的集成电路和操作集成电路的方法

    公开(公告)号：US20110122709A1

    公开(公告)日：2011-05-26

    申请号：US12801502

    申请日：2010-06-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    IPC分类号： G11C7/10 ,  H03K19/173

    CPC分类号： H03K19/1733 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/356008

    摘要： A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.

    摘要翻译： 非易失性逻辑电路包括：锁存单元，包括一对第一和第二锁存节点; 以及分别电连接到第一和第二锁存节点的一对第一和第二非易失性存储单元。 当写入使能信号被激活时，根据流过第一和第二非易失性存储器单元的电流的方向在第一和第二非易失性存储器单元上执行写入操作。 基于相应的第一和第二锁存节点上的数据确定的电流的流动方向和写在第一非易失性存储器单元上的逻辑值与写入第二非易失性存储单元的逻辑值不同。