公开(公告)号：US20250105136A1

公开(公告)日：2025-03-27

申请号：US18473887

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel A. Elsherbini ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Thomas Lee Sounart ,  Tushar Kanti Talukdar ,  Johanna Marie Swan ,  Uygar Avci

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: Capacitors for use with integrated circuit packages are disclosed. An example apparatus includes a semiconductor substrate, a metal layer coupled to the semiconductor substrate, a dielectric layer coupled to the metal layer, the dielectric layer including a capacitor disposed therein, and an interface layer positioned between the metal layer and the dielectric layer, the interface layer in contact with the dielectric layer and in contact with the metal layer.

公开(公告)号：US12166122B2

公开(公告)日：2024-12-10

申请号：US17133197

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Uygar Avci ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Sou-Chi Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

公开(公告)号：US20240222485A1

公开(公告)日：2024-07-04

申请号：US18091209

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Tristan Tronic ,  Chelsey Dorow ,  Kevin O?Brien ,  Uygar Avci ,  Carl H. Naylor ,  Chia-Ching Lin ,  Dominique Adams ,  Matthew Metz ,  Ande Kitamura ,  Scott B. Clendenning

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/26 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/26 ,  H01L29/42392 ,  H01L29/66969

Abstract: A transistor structure includes a stack of nanoribbons coupling source and drain terminals. The nanoribbons may each include a pair of crystalline interface layers and a channel layer between the interface layers. The channel layers may be a molecular monolayer, including a metal and a chalcogen, with a thickness of less than 1 nm. The channel layers may be substantially monocrystalline, and the interface layers may be lattice matched to the channel layers. The channel layers may be epitaxially grown over the lattice-matched interface layers. The crystalline interface layers may be grown over sacrificial layers when forming the stack of nanoribbons.

公开(公告)号：US11727260B2

公开(公告)日：2023-08-15

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22 ,  G06N3/065 ,  H10B10/00 ,  H10B12/00 ,  H10B53/00

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C11/54 ,  H10B10/18 ,  H10B12/01 ,  H10B12/033 ,  H10B12/20 ,  H10B12/50 ,  H10B53/00 ,  G11C11/221 ,  G11C11/409 ,  G11C11/419

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20230253475A1

公开(公告)日：2023-08-10

申请号：US18130334

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H03H9/17 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/7851 ,  H03H9/17 ,  H01L29/78391 ,  H01L29/42356

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

公开(公告)号：US20230200082A1

公开(公告)日：2023-06-22

申请号：US17558429

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek Anil Sharma ,  Uygar Avci

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Integrated circuits with embedded memory that includes double-walled ferroelectric capacitors over an array of access transistors. Capacitor access transistors may be recessed channel array transistors (RCATs) implemented in a monocrystalline material that has been transferred from a donor wafer, or implemented in an amorphous or polycrystalline semiconductor material that has been deposited, such as a metal oxide semiconductor.

公开(公告)号：US20230197654A1

公开(公告)日：2023-06-22

申请号：US17558446

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Abhishek Anil Sharma ,  Uygar Avci

IPC: H01L23/00 ,  H01L27/11507 ,  H01L27/11509 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L27/11507 ,  H01L27/11509 ,  H01L24/80 ,  H01L28/55 ,  H01L27/10814

Abstract: Integrated circuits with embedded memory having multiple levels. Each memory array level includes ferroelectric capacitors coupled to an array of thin film access transistors according to a 1T-1F or 1T-many F bit-cell architecture. The levels of embedded memory are monolithically fabricated, one over the other, or after monolithically fabricating one level of embedded memory in a host IC structure, a second IC structure with another level of memory array is directly bonded to a front or backside of the host IC structure in a face-to-face or face-to-back orientation. The second IC structure may include additional peripheral CMOS circuitry, such as sense amps or decoders, or not.

公开(公告)号：US20220199783A1

公开(公告)日：2022-06-23

申请号：US17133087

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Tanay Gosavi ,  Sudarat Lee ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Uygar Avci

IPC: H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/22 ,  H01L27/24

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

公开(公告)号：US20220199619A1

公开(公告)日：2022-06-23

申请号：US17133208

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Seung Hoon Sung ,  Jack Kavalieros ,  Uygar Avci ,  Tristan Tronic ,  Shriram Shivaraman ,  Devin Merrill ,  Tobias Brown-Heft ,  Kirby Maxey ,  Matthew Metz ,  Ian Young

IPC: H01L27/092 ,  H01L27/22 ,  H01L27/24 ,  H01L43/02 ,  H01L43/08 ,  H01L45/00 ,  H01L43/12

Abstract: A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf1-xZxO2, where 0.33

公开(公告)号：US20210408224A1

公开(公告)日：2021-12-30

申请号：US16914161

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  I-Cheng Tung ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Matthew Metz ,  Uygar Avci

IPC: H01L49/02 ,  H01L27/06

Abstract: A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.