公开(公告)号：US10922079B2

公开(公告)日：2021-02-16

申请号：US15856245

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Kirk S. Yap ,  James Guilford ,  Simon N. Peffers

IPC: G06F9/00 ,  G06F9/30 ,  G06F16/2455 ,  G06F16/2453 ,  G06F16/245

Abstract: Data element filter logic (“hardware accelerator”) in a processor that offloads computation for an in-memory database select/extract operation from a Central Processing Unit (CPU) core in the processor is provided. The Data element filter logic provides a balanced performance across an entire range of widths (number of bits) of data elements in a column-oriented Database Management System.

公开(公告)号：US20200328879A1

公开(公告)日：2020-10-15

申请号：US16946470

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Raghunandan Makaram ,  Ishwar Agarwal ,  Kirk S. Yap ,  Nitish Paliwal ,  David J. Harriman ,  Ioannis T. Schoinas

IPC: H04L9/06 ,  G06F21/62 ,  H04L1/18

Abstract: An apparatus includes a port with circuitry to implement one or more layers of a Compute Express Link (CXL)-based protocol. The port includes an agent to obtain information to be transmitted to another device over a link based on the CXL-based protocol via a flit, encrypt at least a portion of the information to yield a ciphertext, generate a cyclic redundancy check (CRC) code based on the ciphertext, and cause a flit to be generated comprising the ciphertext. The port is to use the circuitry to transmit the flit and the CRC code to the other device over the link.

公开(公告)号：US10592245B2

公开(公告)日：2020-03-17

申请号：US15600200

申请日：2017-05-19

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Sean M. Gulley ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: G06F9/30 ,  G06F21/72

Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.

公开(公告)号：US10530568B2

公开(公告)日：2020-01-07

申请号：US15457004

申请日：2017-03-13

Applicant: INTEL CORPORATION

Inventor： Eugene M. Kishinevsky ,  Uday R. Savagaonkar ,  Alpa T. Narendra Trivedi ,  Siddhartha Chhabra ,  Baiju V. Patel ,  Men Long ,  Kirk S. Yap ,  David M. Durham

IPC: H04L9/12 ,  H04L9/06 ,  G06F12/14 ,  G09C1/00 ,  G06F21/85 ,  G06F21/60 ,  G06F12/0868

Abstract: Encryption interface technologies are described. A processor can include a system agent, an encryption interface, and a memory controller. The system agent can communicate data with a hardware functional block. The encryption interface can be coupled between the system agent and a memory controller. The encryption interface can receive a plaintext request from the system agent, encrypt the plaintext request to obtain an encrypted request, and communicate the encrypted request to the memory controller. The memory controller can communicate the encrypted request to a main memory of the computing device.

公开(公告)号：US10331451B2

公开(公告)日：2019-06-25

申请号：US15396572

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F21/60 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/0897 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G09C1/00 ,  H04L9/32 ,  G06F15/80 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US10331450B2

公开(公告)日：2019-06-25

申请号：US15396563

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: G06F21/60 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/0897 ,  G06F13/28 ,  G06F13/40 ,  G06F13/42 ,  G09C1/00 ,  H04L9/32 ,  G06F15/80 ,  H04L9/06

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20190182032A1

公开(公告)日：2019-06-13

申请号：US16208542

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

IPC: H04L9/06 ,  G06F15/80 ,  G06F21/60 ,  G06F21/64 ,  G06F9/30 ,  G06F9/38

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/8007 ,  G06F21/602 ,  G06F21/64

Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

公开(公告)号：US10263637B2

公开(公告)日：2019-04-16

申请号：US15854261

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap

IPC: H03M7/30 ,  H03M7/40 ,  B65G1/04 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F3/06 ,  G06F8/65 ,  G06F9/50 ,  G07C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04Q1/04 ,  H04W4/02 ,  H05K7/14 ,  G06F13/40 ,  H05K5/02 ,  G08C17/02 ,  H04L12/24 ,  H04L29/08 ,  H04L12/26 ,  H04L12/851 ,  H04Q11/00 ,  H04L12/911 ,  G06F12/109 ,  H04L29/06 ,  G11C14/00 ,  G11C11/56 ,  G06F12/14 ,  G06F13/16 ,  H04B10/25 ,  G06F9/4401 ,  B25J15/00 ,  H05K7/20 ,  H04L12/931 ,  H04L12/939 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  G06F12/0893 ,  H05K13/04 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  G06F17/30 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  H04L12/28 ,  H04L29/12 ,  H04L12/933 ,  H04L12/947 ,  H04W4/80 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04

Abstract: Technologies for performing speculative decompression include a managed node to decode a variable size code at a present position in compressed data with a deterministic decoder and concurrently perform speculative decodes over a range of subsequent positions in the compressed data, determine the position of the next code, determine whether the position of the next code is within the range, and output, in response to a determination that the position of the next code is within the range, a symbol associated with the deterministically decoded code and another symbol associated with a speculatively decoded code at the position of the next code.

公开(公告)号：US10224959B2

公开(公告)日：2019-03-05

申请号：US15935117

申请日：2018-03-26

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Daniel F. Cutter ,  Wajdi K. Feghali

IPC: H03M7/40 ,  H03M7/30 ,  H04L1/24

Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

公开(公告)号：US10191684B2

公开(公告)日：2019-01-29

申请号：US15719735

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Kirk S. Yap ,  Daniel F. Cutter ,  Wajdi K. Feghali

IPC: H03M7/30 ,  G06F3/06 ,  G06F17/30 ,  H03M7/40 ,  H04L12/26 ,  H04L12/813 ,  H04L12/851 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34 ,  G06F7/06 ,  G06T9/00 ,  H03M7/42 ,  H04L12/28 ,  H04L12/46 ,  H04L29/12 ,  G06F13/16 ,  G06F21/62 ,  G06F21/76 ,  H03K19/173 ,  H04L9/08 ,  H04L12/933 ,  H04L29/08 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06T1/20 ,  G06T1/60 ,  G06F9/54 ,  G06F8/656 ,  G06F8/658 ,  G06F8/654 ,  G06F9/4401 ,  H01R13/453 ,  H01R13/631 ,  H05K7/14 ,  G06F21/57 ,  G06F21/73 ,  G06F8/65 ,  G06F11/14 ,  G06F12/02 ,  H04L12/24 ,  H04L29/06 ,  G06F15/80

Abstract: Technologies for flexibly compressing data include a computing device having an accelerator complex that is to receive a compression job request and schedule the compression job request for one or more hardware compression resources of the accelerator complex. The accelerator complex is further to perform the compression job request with the one or more hardware compression resources in response to scheduling the compression job request and to communicate uncompressed data and compressed data with an I/O subsystem of the computing device in response to performing the compression job request. Other embodiments are described and claimed.