公开(公告)号：US20170273187A1

公开(公告)日：2017-09-21

申请号：US15074064

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Rahul Jain ,  Robert Alan May ,  Sheng Li ,  Sri Ranga Sai Boyapati

IPC: H05K3/00 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K3/0041 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/0055 ,  H05K3/3452 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  H05K2203/0588 ,  H05K2203/095

Abstract: A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.

公开(公告)号：US12300613B2

公开(公告)日：2025-05-13

申请号：US18525435

申请日：2023-11-30

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Kristof Darmawikarta ,  Sri Ranga Sai Sai Boyapati

IPC: H01L23/532 ,  H01L23/29 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H01L23/538 ,  H01L25/00

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240114627A1

公开(公告)日：2024-04-04

申请号：US17937894

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Robert Alan May ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram ,  Brandon C. Marin

IPC: H05K3/06 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09

CPC classification number: H05K3/062 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H05K1/09 ,  H05K3/067 ,  H01L25/0652

Abstract: Embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. The first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.

公开(公告)号：US11923307B2

公开(公告)日：2024-03-05

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20240030142A1

公开(公告)日：2024-01-25

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/367 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/16 ,  H01L23/5384 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20230420412A1

公开(公告)日：2023-12-28

申请号：US17847434

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Kristof Kuwawi Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L25/0652 ,  H01L23/5385 ,  H01L24/16 ,  H01L23/5384 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/32 ,  H01L24/73 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29294 ,  H01L2224/29293

Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a package substrate; an interposer coupled to the package substrate, the interposer comprising a dielectric material, a conductive pillar) through the dielectric material and a conductive structure at least partially surrounding the conductive pillar, the conductive structure separated from the conductive pillar by the dielectric material; and an integrated circuit (IC) die coupled to the interposer on a side opposite to the package substrate. The conductive pillar conductively couples the IC die to the package substrate, and the conductive structure is coupled to a ground connection.

公开(公告)号：US11688692B2

公开(公告)日：2023-06-27

申请号：US17540079

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Praneeth Kumar Akkinepally ,  Frank Truong ,  Jason M. Gamba ,  Robert Alan May

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

公开(公告)号：US11508662B2

公开(公告)日：2022-11-22

申请号：US16322423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert Alan May ,  Wei-Lun Kane Jen ,  Jonathan L. Rosch ,  Islam A. Salama ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

公开(公告)号：US11309239B2

公开(公告)日：2022-04-19

申请号：US17075533

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Jung Kyu Han ,  Ali Lehaf ,  Steve Cho ,  Thomas Heaton ,  Hiroki Tanaka ,  Kristof Darmawikarta ,  Robert Alan May ,  Sri Ranga Sai Boyapati

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.