公开(公告)号：US4458162A

公开(公告)日：1984-07-03

申请号：US282110

申请日：1981-07-10

申请人： Paul M. Solomon ,  Siegfried K. Wiedmann

发明人： Paul M. Solomon ,  Siegfried K. Wiedmann

IPC分类号： H03K17/60 ,  H03K19/00 ,  H03K19/013 ,  H03K19/088

CPC分类号： H03K19/088 ,  H03K19/001 ,  H03K19/013

摘要： A Transistor-Transistor Logic (TTL) gate is disclosed wherein a different amount of base current is applied to the inverter transistor than is applied to the base of the output transistor. In one embodiment, a current mirror circuit controls the amount of base current flowing between the input transistor collector terminal and the base terminal of the inverter transistor to an amount less than that flowing between the input transistor collector terminal and the base terminal of the output transistor. In another embodiment, a resistor in series with the base of the inverter transistor performs the same function as the current mirror circuit.

摘要翻译： 公开了晶体管 - 晶体管逻辑（TTL）门，其中与施加到输出晶体管的基极相比，不同量的基极电流被施加到反相器晶体管。 在一个实施例中，电流镜电路控制在反相器晶体管的输入晶体管集电极端子和基极端子之间流动的基极电流量小于在输入晶体管集电极端子和输出晶体管的基极端子之间流动的基极电流量 。 在另一实施例中，与逆变器晶体管的基极串联的电阻器执行与电流镜电路相同的功能。

公开(公告)号：US09099327B2

公开(公告)日：2015-08-04

申请号：US13568839

申请日：2012-08-07

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L29/417

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

摘要翻译： 一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻 并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

公开(公告)号：US20120326605A1

公开(公告)日：2012-12-27

申请号：US13603110

申请日：2012-09-04

申请人： Paul M. Solomon

发明人： Paul M. Solomon

IPC分类号： H01J25/10 ,  B82Y99/00

CPC分类号： H01J25/10 ,  B82Y10/00

摘要： A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.

摘要翻译： 通过在导线的两端形成源极接触和漏极接触并且在导线上形成偏置栅极和信号栅极来制造固态速调管结构。 导线可以是至少一个碳纳米管或具有长的弹道平均自由路径的至少一个半导体线。 通过以对应于信号栅极的相邻指状物之间的弹道载体的渡越时间的整数倍的频率施加信号，载流子在导线内聚束，从而以一定频率放大通过固态速调管的电流 信号到信号门，从而实现功率增益。

公开(公告)号：US08258031B2

公开(公告)日：2012-09-04

申请号：US12815902

申请日：2010-06-15

申请人： Isaac Lauer ,  Amlan Majumdar ,  Paul M. Solomon ,  Steven J. Koester

发明人： Isaac Lauer ,  Amlan Majumdar ,  Paul M. Solomon ,  Steven J. Koester

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/165 ,  H01L29/7391

摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

摘要翻译： 示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区 邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

公开(公告)号：US20120193678A1

公开(公告)日：2012-08-02

申请号：US13430041

申请日：2012-03-26

申请人： Isaac Lauer ,  Amlan Majumdar ,  Paul M. Solomon ,  Steven J. Koester

发明人： Isaac Lauer ,  Amlan Majumdar ,  Paul M. Solomon ,  Steven J. Koester

IPC分类号： H01L29/78 ,  H01L21/335

CPC分类号： H01L29/165 ,  H01L29/7391

摘要： Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

摘要翻译： 示例性实施例包括用于制造异质结隧道场效应晶体管（FET）的方法，所述方法包括在绝缘体上硅（SOI）衬底的硅层上形成栅区，在硅层上形成漏极区 邻近所述栅极区域并形成与所述栅极区域相邻的垂直异质结源区域，其中所述垂直异质结源区域产生与所述栅极区域相关联的栅极场列的隧道路径。

公开(公告)号：US20110049474A1

公开(公告)日：2011-03-03

申请号：US12550857

申请日：2009-08-31

申请人： Mikael T. Bjoerk ,  Siegfried F. Karg ,  Joachim Knoch ,  Heike E. Reil ,  Walter H. Riess ,  Paul M. Solomon

发明人： Mikael T. Bjoerk ,  Siegfried F. Karg ,  Joachim Knoch ,  Heike E. Reil ,  Walter H. Riess ,  Paul M. Solomon

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/7391 ,  B82Y10/00 ,  H01L29/0665

摘要： An indirectly induced tunnel emitter for a tunneling field effect transistor (TFET) structure includes an outer sheath that at least partially surrounds an elongated core element, the elongated core element formed from a first semiconductor material; an insulator layer disposed between the outer sheath and the core element; the outer sheath disposed at a location corresponding to a source region of the TFET structure; and a source contact that shorts the outer sheath to the core element; wherein the outer sheath is configured to introduce a carrier concentration in the source region of the core element sufficient for tunneling into a channel region of the TFET structure during an on state.

摘要翻译： 用于隧道场效应晶体管（TFET）结构的间接感应隧道发射器包括至少部分地围绕细长芯元件的外护套，所述细长芯元件由第一半导体材料形成; 设置在所述外护套和所述芯元件之间的绝缘体层; 所述外护套设置在对应于所述TFET结构的源极区域的位置处; 以及将外护套短路到芯元件的源极接触件; 其中所述外护套被配置为在所述芯部元件的源极区域中引入足够的载流子浓度以在导通状态期间隧穿到所述TFET结构的沟道区域。

公开(公告)号：US20090124057A1

公开(公告)日：2009-05-14

申请号：US12354088

申请日：2009-01-15

申请人： Supratik Guha ,  Hussein I. Hanafi ,  Rajarao Jammy ,  Paul M. Solomon

发明人： Supratik Guha ,  Hussein I. Hanafi ,  Rajarao Jammy ,  Paul M. Solomon

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/2652 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28229 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

摘要： A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure.

摘要翻译： 公开了一种MOSFET，其包括在源极延伸部和漏极延伸部之间的沟道，沟道上的介电层，形成在电介质层的外围部分上的栅极间隔结构，以及形成在该介电层的非外围部分上的栅极 电介质层，其栅极的至少一部分被栅极间隔结构的内表面包围并与栅极间隔结构的内表面接触，并且栅极在其底部基本上与沟道对准。 形成MOSFET的一种方法包括在通过去除牺牲栅极和间隔物结构形成的空腔内部形成介电层，栅极间隔物结构和栅极接触。

公开(公告)号：US07459752B2

公开(公告)日：2008-12-02

申请号：US11473757

申请日：2006-06-23

申请人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

发明人： Bruce B. Doris ,  Meikei Ieong ,  Zhibin Ren ,  Paul M. Solomon ,  Min Yang

IPC分类号： H01L27/12

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772

摘要： Ultra thin body fully-depleted silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations are provided. Such a SOI MOSFET may include a SOI substrate having a SOI layer in which a first portion thereof has a thickness of less than 20 nm; a gate including a gate dielectric and a gate electrode located atop the first portion of the SOI layer having the thickness, the gate electrode having an upper surface and a bottom surface that have the same length or the bottom surface has a length that is greater than the upper surface; and source and drain diffusion regions located in a second portion of the SOI layer that is adjacent to the first portion, and the second portion of the SOI layer is thicker than the first portion.

摘要翻译： 超薄体绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET），其中SOI厚度随栅极长度变化而变化，从而最小化通常由SOI引起的阈值电压变化 提供了厚度和栅极长度的变化。 这样的SOI MOSFET可以包括具有SOI层的SOI衬底，其中第一部分的厚度小于20nm; 包括栅电介质的栅极和位于具有厚度的SOI层的第一部分顶部的栅电极，栅极具有具有相同长度或底表面的上表面和底表面，其长度大于 上表面 以及位于SOI层的与第一部分相邻的第二部分中的源极和漏极扩散区，并且SOI层的第二部分比第一部分厚。

公开(公告)号：US20080293246A1

公开(公告)日：2008-11-27

申请号：US12167686

申请日：2008-07-03

申请人： Guy Moshe Cohen ,  Paul M. Solomon

发明人： Guy Moshe Cohen ,  Paul M. Solomon

IPC分类号： H01L21/44

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02653 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828 ,  Y10S977/762 ,  Y10S977/938

摘要： A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance.

摘要翻译： 公开了一种具有形成FET沟道的纳米线的垂直FET结构。 纳米线形成在导电硅化物层上。 纳米线由周围的门浇口。 顶部和底部绝缘体插塞用作栅极间隔，并减少栅极 - 源极和栅极 - 漏极电容。

公开(公告)号：US20080286930A1

公开(公告)日：2008-11-20

申请号：US12142394

申请日：2008-06-19

申请人： Kevin K. Chan ,  Hussein I. Hanafi ,  Paul M. Solomon

发明人： Kevin K. Chan ,  Hussein I. Hanafi ,  Paul M. Solomon

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. In the present invention, self-aligned isolation regions are provided to reduce the parasitic capacitance in the DGFET structure. Additionally, the present invention encapsulates the silicon-containing channel layer to enable the back-gate to be oxidized to a greater extent thereby reducing the parasitic capacitance of the structure even further.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 在本发明中，提供自对准隔离区以减小DGFET结构中的寄生电容。 此外，本发明封装了含硅沟道层，使背栅能够被更大程度地氧化，从而进一步降低结构的寄生电容。