公开(公告)号：US06597068B2

公开(公告)日：2003-07-22

申请号：US10034862

申请日：2001-12-28

申请人： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

发明人： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC分类号： H01L2348

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

摘要： A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

公开(公告)号：US06368953B1

公开(公告)日：2002-04-09

申请号：US09567466

申请日：2000-05-09

申请人： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

发明人： Kevin S. Petrarca ,  Donald Canaperi ,  Mahadevaiyer Krishnan ,  Kenneth Jay Stein ,  Richard P. Volant

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/7684 ,  H01L28/60

摘要： A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.

摘要翻译： 描述了一种在衬底中形成的特征中制造封装金属结构的方法。 特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。 在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。 优选通过化学机械抛光将附加阻挡层平坦化。 该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。 第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。 介电层沉积在开口中，覆盖其底部的封装金属结构。 作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。 介电层和附加层优选通过CMP平坦化。

公开(公告)号：US06368484B1

公开(公告)日：2002-04-09

申请号：US09567468

申请日：2000-05-09

申请人： Richard P. Volant ,  Peter S. Locke ,  Kevin S. Petrarca ,  David M. Rockwell ,  Seshadri Subbanna

发明人： Richard P. Volant ,  Peter S. Locke ,  Kevin S. Petrarca ,  David M. Rockwell ,  Seshadri Subbanna

IPC分类号： C25D548

CPC分类号： H01L21/76865 ,  C25D5/02 ,  C25D5/48 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879

摘要： A method is described for electroplating a metal structure in a feature formed in a substrate. A seed layer of the metal is deposited on the top surface and on the bottom and sidewalls of the feature. The seed layer is then selectively removed from the top surface, so that only a portion of the seed layer remains in the feature on at least the bottom thereof. The metal is then electroplated using this portion of the seed layer, so that the metal fills the feature. The removal of the seed layer from the top surface causes no electroplating to occur on the top surface.

摘要翻译： 描述了一种用于在形成在基底中的特征中电镀金属结构的方法。 金属的种子层沉积在特征的顶表面和底部以及侧壁上。 然后，从顶表面选择性地去除晶种层，使得至少其底部仅有部分种子层保留在特征中。 然后使用种子层的这一部分电镀金属，使得金属填充该特征。 从上表面去除种子层不会在顶表面上发生电镀。

公开(公告)号：US20140061915A1

公开(公告)日：2014-03-06

申请号：US13599295

申请日：2012-08-30

申请人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

发明人： Christopher N. Collins ,  Daniel C. Edelstein ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Andrew H. Simon ,  Richard P. Volant

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/76873 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/8001 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A method of forming an integrated circuit device includes forming a diffusion barrier layer in an opening defined in a substrate; forming a highly doped copper alloy seed layer over the diffusion barrier layer, the copper alloy seed layer having a minority alloy component having a concentration greater than 0.5% atomic; and forming a copper layer over the copper alloy seed layer so as to define a wiring structure of the integrated circuit device.

摘要翻译： 形成集成电路器件的方法包括在限定在衬底中的开口中形成扩散阻挡层; 在所述扩散阻挡层上形成高掺杂的铜合金种子层，所述铜合金种子层具有浓度大于0.5％原子的少数合金成分; 以及在所述铜合金晶种层上形成铜层，以限定所述集成电路器件的布线结构。

公开(公告)号：US20110080189A1

公开(公告)日：2011-04-07

申请号：US12574264

申请日：2009-10-06

申请人： Oleg Gluschenkov ,  Muthukumarasamy Karthikeyan ,  Yunsheng Song ,  Tso-Hui Ting ,  Richard P. Volant ,  Ping-Chuan Wang

发明人： Oleg Gluschenkov ,  Muthukumarasamy Karthikeyan ,  Yunsheng Song ,  Tso-Hui Ting ,  Richard P. Volant ,  Ping-Chuan Wang

IPC分类号： G01R31/26 ,  H01L23/00 ,  G01R31/02

CPC分类号： G01R1/07378 ,  H01L22/14 ,  H01L22/20 ,  H01L25/50 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A set of first substrate and second substrate are manufactured with a built-in N-fold rotational symmetry around the center axis of each substrate, wherein N is an integer greater than 1. A set of N different interposers is provided such that an i-th interposer provides electrical connection between the first substrate and the second substrate with a rotational angle of (i−1)/N×2π. The first and second substrates are tested with each of the N different interposers therebetween. Once the rotational angle that provides the highest stacked chip yield is determined, the first and the second substrates can be bonded with an azimuthal rotation that provides the highest stacked chip yield.

摘要翻译： 一组第一衬底和第二衬底被制造成围绕每个衬底的中心轴线具有内置的N倍旋转对称，其中N是大于1的整数。提供一组N个不同的插入件， （i-1）/ N×2＆pgr的转角提供第一基板和第二基板之间的电连接。 测试第一和第二衬底中的每个N个不同的插入件。 一旦确定了提供最高堆叠芯片产量的旋转角度，则可以以提供最高堆叠芯片产量的方位角旋转来接合第一和第二基板。

公开(公告)号：US07670921B2

公开(公告)日：2010-03-02

申请号：US11616955

申请日：2006-12-28

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

IPC分类号： H01L21/4763

CPC分类号： H01G4/33 ,  H01G4/005 ,  H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/417 ,  H01L2924/00

摘要： A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.

摘要翻译： 形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图和保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。

公开(公告)号：US07622357B2

公开(公告)日：2009-11-24

申请号：US11420282

申请日：2006-05-25

申请人： Kunal Vaed ,  Jae-Sung Rieh ,  Richard P. Volant ,  Francois Pagette

发明人： Kunal Vaed ,  Jae-Sung Rieh ,  Richard P. Volant ,  Francois Pagette

IPC分类号： H01L21/331

CPC分类号： H01L29/7371 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The present invention relates to a device structure that comprises a substrate with front and back surfaces, and at least one semiconductor device with a first conductive structure located in the substrate and a second conductive structure located thereover. A first conductive contact is located over the front surface of the substrate and laterally offset from the first conductive structure. The first conductive contact is electrically connected to the first conductive structure by a conductive path that extends: (1) from the first conductive structure through the substrate to the back surface, (2) across the back surface, and (3) from the back surface through the substrate to the first conductive contact on the front surface. Further, a second conductive contact is located over the front surface and is electrically connected to the second conductive structure. The conductive path can be formed by lithography and etching followed by metal deposition.

摘要翻译： 本发明涉及一种器件结构，其包括具有前表面和后表面的衬底，以及至少一个具有位于衬底中的第一导电结构的半导体器件和位于其上的第二导电结构。 第一导电接触位于衬底的前表面上并且横向偏离第一导电结构。 第一导电接触件通过导电路径电连接到第一导电结构，导电路径延伸：（1）从第一导电结构通过基底延伸到背面，（2）延伸穿过后表面，和（3）从背面 通过基板的表面到前表面上的第一导电接触。 此外，第二导电触点位于前表面上并且电连接到第二导电结构。 导电路径可以通过光刻和蚀刻形成，之后是金属沉积。

公开(公告)号：US07602265B2

公开(公告)日：2009-10-13

申请号：US11163485

申请日：2005-10-20

申请人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

发明人： Hariklia Deligianni ,  Robert D. Edwards ,  Thomas J. Fleischman ,  Robert A. Groves ,  Charles J. Montrose ,  Richard P. Volant ,  Ping-Chuan Wang

IPC分类号： H01H51/22

CPC分类号： H01H59/0009

摘要： The present invention provides multiple test structures for performing reliability and qualification tests on MEMS switch devices. A Test structure for contact and gap characteristic measurements is employed having a serpentine layout simulates rows of upper and lower actuation electrodes. A cascaded switch chain test is used to monitor process defects with large sample sizes. A ring oscillator is used to measure switch speed and switch lifetime. A resistor ladder test structure is configured having each resistor in series with a switch to be tested, and having each switch-resistor pair electrically connected in parallel. Serial/parallel test structures are proposed with MEMS switches working in tandem with switches of established technology. A shift register is used to monitor the open and close state of the MEMS switches. Pull-in voltage, drop-out voltage, activation leakage current, and switch lifetime measurements are performed using the shift register.

摘要翻译： 本发明提供用于在MEMS开关装置上执行可靠性和鉴定测试的多个测试结构。 采用具有蛇形布局的接触和间隙特性测量的测试结构来模拟上下驱动电极的行。 级联交换链测试用于监控大样本量的过程缺陷。 环形振荡器用于测量开关速度和开关寿命。 电阻梯形测试结构被配置为具有与要测试的开关串联的每个电阻器，并且每个开关电阻器对并联电连接。 提出了串联/并联测试结构，其中MEMS开关与成熟技术的开关串联工作。 移位寄存器用于监测MEMS开关的开启和关闭状态。 使用移位寄存器执行拉入电压，掉电电压，启动漏电流和开关寿命测量。

公开(公告)号：US20090181532A1

公开(公告)日：2009-07-16

申请号：US11971996

申请日：2008-01-10

申请人： David P. Colon ,  Bradley P. Jones ,  Ramona Kei ,  Raymond G. Knauss ,  Richard P. Volant ,  Yun-Yu Wang

发明人： David P. Colon ,  Bradley P. Jones ,  Ramona Kei ,  Raymond G. Knauss ,  Richard P. Volant ,  Yun-Yu Wang

IPC分类号： H01L21/44

CPC分类号： H01L24/03 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/00014

摘要： An interconnect structure having an incomplete via opening is processed to deepen a via opening and to expose a metal line. In case the interconnect structure comprises a metal pad or a blanket metal layer, the metal pad or the metal layer is removed selective to an underlying dielectric layer to expose the incomplete via opening. Another dielectric layer is formed within the incomplete via opening to compensated for differences in the total dielectric thickness above the metal line relative to an optimal dielectric stack. A photoresist is applied thereupon and patterned. An anisotropic etch process for formation of a normal via opening may be employed with no or minimal modification to form a proper via opening and to expose the metal line. A metal pad is formed upon the metal line so that electrical contact is provided between the metal pad and the metal line.

摘要翻译： 处理具有不完全通孔的互连结构以加深通孔开口并露出金属线。 在互连结构包括金属焊盘或覆盖金属层的情况下，金属焊盘或金属层被选择性地移除到下面的电介质层以暴露不完全通孔。 在不完全通孔内部形成另一个介电层，以补偿相对于最佳电介质叠层的金属线上方的总电介质厚度的差异。 在其上施加光致抗蚀剂并图案化。 可以采用用于形成正常通孔的各向异性蚀刻工艺，没有或最小的修改以形成适当的通孔开口并露出金属线。 在金属线上形成金属焊盘，使得金属焊盘和金属线之间提供电接触。

公开(公告)号：US07480538B2

公开(公告)日：2009-01-20

申请号：US11939792

申请日：2007-11-14

申请人： Richard P. Volant ,  Bradley P. Jones ,  Sameer T. Shikalgar ,  Michael J. Toner ,  Yutong Wu

发明人： Richard P. Volant ,  Bradley P. Jones ,  Sameer T. Shikalgar ,  Michael J. Toner ,  Yutong Wu

IPC分类号： G06F19/00

CPC分类号： G06Q50/04 ,  G06Q10/06 ,  Y02P80/40 ,  Y02P90/30 ,  Y02P90/86

摘要： Methods, systems, and computer program products for managing movement of work-in-process materials between processing units in an automated manufacturing environment are provided. A system includes a host system in communication with a work-in-process (WIP) material lot. The system also includes an application executing on the host. The application implements a method that includes tracking a position of the WIP material lot, receiving a list of the processing units designated to be inoperative during a down time, and receiving a start time and a duration of the down time. The method also includes determining a maximum dwell time for each of the designated processing units and scheduling movement of the WIP material lot during an interim between a current time and the start time of the down time based on current position of the work-in-process material lot, the current time, the start time and duration of the down time, and the maximum dwell time.

摘要翻译： 提供了用于管理在自动化制造环境中的处理单元之间的在制品材料的移动的方法，系统和计算机程序产品。 系统包括与工件在制品（WIP）材料批次通信的主机系统。 该系统还包括在主机上执行的应用程序。 应用程序实现一种方法，其包括跟踪WIP物料批次的位置，接收在停机期间被指定为不起作用的处理单元的列表，以及接收停机时间的开始时间和持续时间。 该方法还包括确定每个指定处理单元的最大驻留时间，并根据当前工作中的位置在当前时间与停机时间的开始时间间隔期间调度WIP材料批次的移动 材料批次，当前时间，停机时间的开始时间和持续时间以及最长停留时间。