公开(公告)号：US09761319B1

公开(公告)日：2017-09-12

申请号：US15344614

申请日：2016-11-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Teng-Hao Yeh ,  Hang-Ting Lue

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445

Abstract: A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.

公开(公告)号：US09490249B2

公开(公告)日：2016-11-08

申请号：US14265635

申请日：2014-04-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Teng-Hao Yeh

IPC: H01L27/06 ,  H01L27/02 ,  H01L23/552 ,  H01L21/8238 ,  H01L27/115

CPC classification number: H01L27/0629 ,  H01L21/823871 ,  H01L23/552 ,  H01L27/0266 ,  H01L27/0292 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antenna effect discharge circuit is described for a device having patterned conductor layers, which may be exposed to charge inducing environments during a manufacturing process. The antenna effect discharge circuit has a terminal that is connected to a node on the device to be protected from charge accumulation and a gate, such as the gate of a field effect transistor in the circuit, and a terminal through which accumulated charge can be discharged to the substrate. A capacitor couples the gate in the antenna effect discharge circuit to the substrate. A voltage supply circuit is configured to provide voltage sufficient to bias the antenna effect discharge circuit in an off condition during operation of the device. A patterned conductor in the upper layer, and preferably the uppermost layer, of the device links the gate in the antenna effect discharge circuit to the voltage supply circuit.

Abstract translation: 对于具有图案化导体层的器件描述了天线效应放电电路，其可能在制造过程中暴露于电荷诱导环境。 天线效应放电电路具有连接到要保护的装置上的节点免受电荷累积的端子和诸如电路中的场效应晶体管的栅极的栅极以及可以放电累积电荷的端子 到基底。 电容器将天线效应放电电路中的栅极耦合到衬底。 电压供给电路被配置为在设备的操作期间提供足以将天线效应放电电路偏置在关闭状态的电压。 该设备的上层，优选最上层的图案化导体将天线效应放电电路中的栅极连接到电压供应电路。

公开(公告)号：US09349745B2

公开(公告)日：2016-05-24

申请号：US14555372

申请日：2014-11-26

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423 ,  H01L21/768 ,  H01L23/528 ,  G11C16/26 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/08 ,  G11C16/26 ,  H01L21/28282 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a plurality of stacks of conductive strips, a plurality of word lines over and orthogonal to the plurality of stacks of conductive strips, a plurality of vertical gate columns, and control circuitry. The plurality of word lines is electrically coupled to the plurality of vertical gate columns acting as gates controlling current flow in the plurality of stacks of conductive strips. The plurality of word lines including a first word line and a second word line adjacent to each other. The plurality of vertical gate columns is between the plurality of stacks of conductive strips. The plurality of vertical gate columns includes a first set of vertical gate columns electrically coupled to the first word line and a second set of vertical gate columns electrically coupled to the second word line. The first set of vertical gate columns is staggered relative to the second set of vertical gate columns. The control circuitry controls the plurality of word lines as gates to control current flow in the plurality of stacks of conductive strips, and controls nonvolatile memory operations.

Abstract translation: 存储器件包括多个导电条的堆叠，多个字线在多个导体条的堆叠之上并且正交于多个堆叠的导电条，多个垂直栅极列和控制电路。 多个字线电耦合到多个垂直栅极柱，其用作控制多个导电条的堆叠中的电流的栅极。 多个字线包括彼此相邻的第一字线和第二字线。 多个垂直门柱位于多个导电片叠之间。 多个垂直门列包括电耦合到第一字线的第一组垂直栅极列和电耦合到第二字线的第二组垂直栅极列。 第一组垂直栅极列相对于第二组垂直栅极列交错。 控制电路控制多个字线作为门，以控制导电条的多个堆叠中的电流，并且控制非易失性存储器操作。

公开(公告)号：US09331204B2

公开(公告)日：2016-05-03

申请号：US14209011

申请日：2014-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7856 ,  H01L29/1041 ,  H01L29/7833 ,  H01L29/7851

Abstract: A high-voltage circuit is described that comprises a high-voltage finFET can have a semiconductor fin with an insulating cap on the fin. A gate dielectric is disposed on the first and second sides of the fin. A gate overlies the gate dielectric and a channel region in the fin on the first and second sides, and over the cap. Source/drain terminals are disposed on opposing sides of the gate in the fin, and can include lightly doped regions that extend away from the edge of the gate to more highly doped contacts. The dimensions of the structures can be configured so that the transistor has a breakdown voltage of 30 V or higher.

Abstract translation: 描述了一种高压电路，其包括高压finFET可以具有在翅片上具有绝缘帽的半导体翅片。 栅极电介质设置在鳍片的第一和第二侧上。 栅极覆盖栅极电介质和第一和第二侧上的鳍中的沟道区域，并且在盖上方。 源极/漏极端子设置在鳍中的栅极的相对侧上，并且可以包括从栅极的边缘延伸到更高掺杂的触点的轻掺杂区域。 可以配置结构的尺寸，使得晶体管具有30V或更高的击穿电压。

公开(公告)号：US09287291B2

公开(公告)日：2016-03-15

申请号：US14852997

申请日：2015-09-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  G11C11/56 ,  G11C16/10 ,  H01L29/51 ,  H01L23/528 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C11/5671 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/511 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A vertical channel 3D NAND array is configured for independent double gate operation, establishing two memory sites per frustum of a vertical channel column, and in addition, for multiple-bit-per-cell operation. The memory device can comprise even and odd stacks of conductive strips. Active pillars are arranged between corresponding even and odd stacks of conductive strips. A 3D array includes even memory cells accessible via the active pillars and conductive strips in the even stacks and odd memory cells accessible via the active pillars and conductive strips in the odd stacks of conductive strips. Control circuitry is configured to apply different bias voltages to the even and odd conductive strips, and execute a program operation by which more than one bit of data is stored in both the even memory cell and odd memory cell in a given frustum of a selected active strip.

Abstract translation: 垂直通道3D NAND阵列被配置用于独立的双栅极操作，每个平截头体垂直通道列建立两个存储器位置，另外，对于每个单元的每个单元的操作。 存储器件可以包括偶数和奇数的导电条带。 有源支柱布置在相应的偶数和奇数的导电条之间。 3D阵列包括通过有源支柱可访问的偶数存储器单元和偶数堆叠中的导电条以及可通过有源支柱访问的奇数存储器单元和导电条的奇数叠层中的导电条。 控制电路被配置为向偶数和奇数导电带施加不同的偏置电压，并且执行编程操作，通过该程序操作，在所选活动的给定平截头体中，多于一位的数据存储在偶数存储单元和奇数存储单元中 跳闸。

公开(公告)号：US09252155B2

公开(公告)日：2016-02-02

申请号：US14309923

申请日：2014-06-20

Applicant: Macronix International Co., Ltd.

Inventor： Tzu-Hsuan Hsu ,  Wei-Chen Chen ,  Hang-Ting Lue

IPC: H01L23/52 ,  H01L27/115 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/225 ,  H01L21/285

CPC classification number: H01L21/28525 ,  H01L21/2257 ,  H01L23/53271 ,  H01L27/11578 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer. A width of the second electrode layer becomes larger in a direction away from the dielectric layer.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括在第一电极层和第二电极层之间的第一电极层，第二电极层和电介质层。 第二电极层的宽度在远离电介质层的方向上变大。

公开(公告)号：US09245603B2

公开(公告)日：2016-01-26

申请号：US14058328

申请日：2013-10-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

IPC: G11C7/14 ,  H01L27/115

CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。

公开(公告)号：US20150371998A1

公开(公告)日：2015-12-24

申请号：US14309622

申请日：2014-06-19

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  H01L29/792

CPC classification number: H01L27/11563 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/66833 ,  H01L29/792

Abstract: A memory cell includes a gate, a channel material having a channel surface and a channel valence band edge, and a dielectric stack between the gate and the channel surface. The dielectric stack comprises a multi-layer tunneling structure on the channel surface, a first charge storage nitride layer on the multi-layer tunneling structure, a first blocking oxide layer on the first charge storage nitride layer, a second charge storage nitride layer on the first blocking dielectric layer, and a second blocking oxide layer on the second charge storage nitride layer. The multi-layer tunneling structure includes a first tunneling oxide layer, a first tunneling nitride layer on the first tunneling oxide layer, and a second tunneling oxide layer on the first tunneling nitride layer.

Abstract translation: 存储单元包括栅极，具有沟道表面和沟道价带边缘的沟道材料，以及栅极和沟道表面之间的介电堆叠。 电介质堆叠包括沟道表面上的多层隧道结构，多层隧道结构上的第一电荷存储氮化物层，第一电荷存储氮化物层上的第一阻挡氧化物层，第一电荷存储氮化物层 第一阻挡介质层和第二电荷存储氮化物层上的第二阻挡氧化物层。 多层隧道结构包括第一隧道氧化物层，第一隧道氧化物层上的第一隧穿氮化物层和第一隧穿氮化物层上的第二隧穿氧化物层。

公开(公告)号：US20140141583A1

公开(公告)日：2014-05-22

申请号：US14166471

申请日：2014-01-28

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Shin-Jang Shen ,  Hang-Ting Lue

IPC: H01L27/115

CPC classification number: H01L27/11578 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76838 ,  H01L27/1021 ,  H01L27/11582

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的多条导电材料形式的脊状叠层，布置成可以通过解码电路耦合到读出放大器的串。 在字符串的公共源选择端的字符串选择处，二极管连接到位线结构。 导电材料条具有在脊形叠层的侧面上的侧表面。 布置成可以连接到行解码器的字线的多条导线垂直地延伸在多个脊形叠层上。 存储器元件位于叠层和导电线上的导电条的侧表面之间的交叉点处的界面区域的多层阵列。

公开(公告)号：US12198770B2

公开(公告)日：2025-01-14

申请号：US17988773

申请日：2022-11-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Chen-Huan Chen ,  Ken-Hui Chen

IPC: G11C16/06 ,  G11C7/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.