公开(公告)号：US20170263556A1

公开(公告)日：2017-09-14

申请号：US15068329

申请日：2016-03-11

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11575

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20140048956A1

公开(公告)日：2014-02-20

申请号：US14066340

申请日：2013-10-29

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US20250157926A1

公开(公告)日：2025-05-15

申请号：US19025392

申请日：2025-01-16

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Graham R. Wolstenholme ,  Aaron S. Yip

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H10B41/00 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/50

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

公开(公告)号：US20250142831A1

公开(公告)日：2025-05-01

申请号：US19004725

申请日：2024-12-30

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H10B43/50 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

公开(公告)号：US12183396B2

公开(公告)日：2024-12-31

申请号：US18096072

申请日：2023-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

公开(公告)号：US20240395326A1

公开(公告)日：2024-11-28

申请号：US18652288

申请日：2024-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Paolo Tessariol ,  Richard J. Hill ,  Aaron S. Yip ,  Kunal Parekh

IPC: G11C16/04 ,  G11C5/06 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Memory array structures might include a data line, a common source, and a plurality of sub-blocks of memory cells selectively connected to the data line and to the common source. Sub-blocks of memory cells might include memory cells formed to be around channel material structures, and might include isolation of source-side select lines of adjacent sub-blocks of memory cells. Methods are included for forming such memory array structures.

公开(公告)号：US20240312535A1

公开(公告)日：2024-09-19

申请号：US18602974

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Paolo Tessariol

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/10

Abstract: Control logic in a memory device causes a plurality of source control signals to be applied to a plurality of deintegrated source segments of a first block of a plurality of blocks of a memory array of a memory device to selectively activate a plurality of sub-blocks of the first block and programs a plurality of select gate devices in a plurality of logical select gate layers spanning the plurality of sub-blocks and positioned at a drain-side of the first block of the memory array with a threshold voltage pattern.

公开(公告)号：US20240237365A1

公开(公告)日：2024-07-11

申请号：US18615718

申请日：2024-03-25

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Paolo Tessariol

IPC: H10B99/00 ,  H01L21/768

CPC classification number: H10B99/00 ,  H01L21/76802 ,  H01L21/76877

Abstract: A method for manufacturing a 3D vertical array of memory cells is disclosed. The method comprises: forming on a substrate a stack of dielectric material layers comprising first and second dielectric material layers alternated to each other; forming holes through the stack of dielectric material layers, said holes exposing the substrate; selectively removing the second material layers through said holes to form cavities between adjacent first dielectric material layers; filling said cavities with a conductive material through said holes to form corresponding conductive material layers; forming first memory cell access lines from said conductive material layers; carrying out a conformal deposition of a chalcogenide material through said holes; forming memory cell storage elements from said deposed chalcogenide material; filling said holes with conductive material to form corresponding second memory cell access lines.

公开(公告)号：US11889695B2

公开(公告)日：2024-01-30

申请号：US17504313

申请日：2021-10-18

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Justin B. Dorhout ,  Indra V. Chary ,  Jun Fang ,  Matthew Park ,  Zhiqiang Xie ,  Scott D. Stull ,  Daniel Osterberg ,  Jason Reece ,  Jian Li

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L29/10 ,  H01L23/522 ,  H10B41/27 ,  H10B43/50 ,  H10B41/35 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/1037 ,  H10B41/27 ,  H10B41/35 ,  H10B43/50 ,  H10B43/10

Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.

公开(公告)号：US20230345730A1

公开(公告)日：2023-10-26

申请号：US18209204

申请日：2023-06-13

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  David H. Wells ,  Umberto Maria Meotto

IPC: H10B43/50 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

CPC classification number: H10B43/50 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.