公开(公告)号：US11101287B2

公开(公告)日：2021-08-24

申请号：US16693507

申请日：2019-11-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

公开(公告)号：US11069708B2

公开(公告)日：2021-07-20

申请号：US16680626

申请日：2019-11-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Wei Jiang ,  Chih-Wei Hu ,  Jia-Rong Chiou

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device and a method for manufacturing the same are provided. A memory device includes a drain pillar structure, a source pillar structure, a charge trapping structure, a vertical channel structure and a gate structure. The drain pillar structure is formed in a first opening. The source pillar structure is formed in a second opening. The vertical channel structure and the vertical channel structure are formed in a hole partially overlapping the first opening and the second opening. The vertical channel structure is divided into two arc channel parts by the drain pillar structure and the source pillar structure. The gate structure surrounds the drain pillar structure, the source pillar structure and the vertical channel structure.

公开(公告)号：US10930669B2

公开(公告)日：2021-02-23

申请号：US16273301

申请日：2019-02-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yu-Wei Jiang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/792 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/28

Abstract: A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

公开(公告)号：US09716137B1

公开(公告)日：2017-07-25

申请号：US15285808

申请日：2016-10-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/52 ,  H01L49/02 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L28/90 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/60

Abstract: An integrated circuit includes 3D memory blocks and 3D capacitor blocks. The 3D capacitor comprises a plurality of stacks of conductive strips alternating with insulating strips, and a first terminal connected to conductive strips in consecutive levels in one or more stacks, whereby the conductive strips act as a first plate of the 3D capacitor. A second terminal is insulated from the first terminal, either connected to conductive strips in consecutive levels in another or other stacks, or connected to a plurality of pillars. No intervening conductive strip is disposed between the conducive strips in consecutive levels.

公开(公告)号：US20160329344A1

公开(公告)日：2016-11-10

申请号：US14704706

申请日：2015-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Lee-Yin Lin

IPC: H01L27/115 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source/drain terminals. The first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals. The first source/drain terminal is electrically coupled to an erase voltage line. The second source/drain terminal is electrically coupled to a corresponding one of a plurality of program/read voltage lines. The third source/drain terminal is electrically coupled to a corresponding one of the plurality of bit lines.

Abstract translation: 与2D基板中的晶体管等2D电压开关晶体管相比，3D NAND存储器阵列的开关晶体管消耗的面积可以减小，具有减小的聚集面积的3D电压开关晶体管。 集成电路包括存储晶体管的3D NAND阵列; 多个位线，其中多个位线中的不同的位线电耦合到3D NAND阵列的不同部分; 以及具有堆叠半导体层的多个晶体管对。 半导体层堆叠中的不同层包括多个晶体管对的不同晶体管对。 多个晶体管对中的每一个包括具有第一，第二和第三源极/漏极端子的第一和第二晶体管。 第一晶体管包括第一和第三源极/漏极端子，第二晶体管包括第二和第三源极/漏极端子。 第一源极/漏极端子电耦合到擦除电压线。 第二源极/漏极端子电耦合到多个编程/读取电压线中的对应的一个。 第三源极/漏极端子电耦合到多个位线中的对应的一个位线。

公开(公告)号：US20160267947A1

公开(公告)日：2016-09-15

申请号：US14645446

申请日：2015-03-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: G11C5/06 ,  H01L27/115 ,  H01L21/768 ,  G11C8/10 ,  H01L23/528

CPC classification number: G11C5/063 ,  G11C8/10 ,  G11C8/14 ,  H01L21/768 ,  H01L23/5283 ,  H01L27/11548 ,  H01L27/11575

Abstract: A 3D memory structure and a method for manufactured the same are provided. The 3D memory structure comprises a plurality of strings, a plurality of first conductive lines, a plurality of second conductive lines and a plurality of third conductive lines. The strings are disposed in parallel. The first conductive lines are disposed over the strings. Center regions of the first conductive lines are disposed perpendicular to the strings. The second conductive lines are disposed over the first conductive lines. The second conductive lines connect end regions of half of the first conductive lines. The third conductive lines are disposed over the second conductive lines. The third conductive lines connect end regions of the other half of the first conductive lines.

Abstract translation: 提供了3D存储器结构及其制造方法。 3D存储器结构包括多个串，多个第一导线，多个第二导线和多个第三导线。 琴弦平行放置。 第一导线设置在弦上。 第一导线的中心区域垂直于弦线设置。 第二导线设置在第一导线上。 第二导线连接一半第一导线的端部区域。 第三导线设置在第二导线上。 第三导线连接第一导电线的另一半的端部区域。

公开(公告)号：US20150109844A1

公开(公告)日：2015-04-23

申请号：US14058328

申请日：2013-10-21

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

IPC: H01L27/105 ,  G11C7/14 ,  G11C5/06

CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。

公开(公告)号：US20140264898A1

公开(公告)日：2014-09-18

申请号：US13948508

申请日：2013-07-23

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/768 ,  H01L21/76838 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/41766 ,  H01L29/788 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Abstract translation: 一种器件包括具有凹陷的基底，具有底部和侧面，从基底的上表面延伸到基底中。 侧面包括横向彼此定向的第一和第二侧面。 交替的有源绝缘层和绝缘层的堆叠覆盖在衬底的表面和凹部上。 活性层中的至少一些具有分别在上表面和下平面上方并且大体上平行于上表面和底部延伸的上部和下部。 有源层具有沿着第一和第二侧定位的第一和第二向上延伸，以从它们各自的有源层的下部延伸。 导电带邻接所述有源层的第二向上延伸。 导电条可以包括在第二向上延伸部分的侧面上的侧壁间隔物，导电条通过层间导体连接到覆盖的导体。

公开(公告)号：US08664761B1

公开(公告)日：2014-03-04

申请号：US13723255

申请日：2012-12-21

Applicant: Macronix International Co., Ltd.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L23/48

CPC classification number: H01L21/76831 ,  H01L21/76816 ,  H01L21/76889 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a plurality of stacked structures and a plurality of contact structures. Each of the stacked structures includes a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. Each of the contact structures is electrically connected to each of the stacked structures. The contact structure includes a first conductive pillar, a dielectric material layer, a metal silicide layer, and a second conductive pillar. The dielectric material layer surrounds the lateral surface of the first conductive pillar. The metal silicide layer is formed on an upper surface of the first conductive pillar. The second conductive pillar is formed on the metal silicide layer. The upper surfaces of the first conductive pillars are coplanar.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括多个堆叠结构和多个接触结构。 每个堆叠结构包括多个导电条和多个绝缘条，并且导电条和绝缘条是交错的。 每个接触结构电连接到每个堆叠结构。 接触结构包括第一导电柱，介电材料层，金属硅化物层和第二导电柱。 介电材料层围绕第一导电柱的侧表面。 金属硅化物层形成在第一导电柱的上表面上。 第二导电柱形成在金属硅化物层上。 第一导电柱的上表面是共面的。