公开(公告)号：US20060172479A1

公开(公告)日：2006-08-03

申请号：US11374939

申请日：2006-03-14

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： H01L21/8234

CPC分类号： H01L29/0653 ,  B82Y10/00 ,  H01L21/28114 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654 ,  H01L29/78684

摘要： Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.

公开(公告)号：US20060166432A1

公开(公告)日：2006-07-27

申请号：US10905881

申请日：2005-01-25

申请人： Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Larry Nesbit

发明人： Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Larry Nesbit

IPC分类号： H01L21/8242

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/3165 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

摘要： A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed to an oxide deposition bath, thereby causing deposition of oxide on those surfaces. Deposition of oxide on the top surface causes growth of the cap layer in a vertical direction and deposition of oxide on the side surface causes growth of the cap layer in a horizontal direction, thereby forming the beanie structure.

摘要翻译： 一种用于形成具有氧化物结构的氧化物半导体器件的方法（在器件的下面突出的氧化物盖）。 首先设置覆盖该部分的氧化物层，该层具有顶表面和侧表面。 然后将顶表面和侧表面暴露于氧化物沉积浴中，从而在这些表面上沉积氧化物。 顶部表面上的氧化物的沉积导致盖层在垂直方向上的生长，并且在侧面上的氧化物的沉积导致盖层在水平方向上的生长，从而形成豆瓣结构。

公开(公告)号：US20060103830A1

公开(公告)日：2006-05-18

申请号：US10904599

申请日：2004-11-18

申请人： Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  Daniel Corliss ,  David Horak ,  Charles Koburger

发明人： Steven Holmes ,  Toshiharu Furukawa ,  Mark Hakey ,  Daniel Corliss ,  David Horak ,  Charles Koburger

IPC分类号： G03B27/58

CPC分类号： G03F7/707 ,  G03F7/70341 ,  G03F7/70808

摘要： An apparatus for holding a wafer and a method for immersion lithography. The apparatus, including a wafer chuck having a central circular vacuum platen, an outer region, and a circular groove centered on the vacuum platen, a top surface of the vacuum platen recessed below a top surface of the outer region and a bottom surface of the groove recessed below the top surface of the vacuum platen; one or more suction ports in the bottom surface of the groove; and a hollow toroidal inflatable and deflatable bladder positioned within the groove.

摘要翻译： 一种用于保持晶片的装置和浸没式光刻方法。 该装置包括具有中心圆形真空压板的圆盘卡盘，外部区域和以真空压板为中心的圆形槽，真空压板的顶表面凹入到外部区域的顶表面之下，底部表面 凹槽凹陷在真空压板的顶表面下方; 在槽的底表面中的一个或多个吸入口; 以及定位在槽内的空心环形充气和可放气的囊。

公开(公告)号：US20060022221A1

公开(公告)日：2006-02-02

申请号：US10901858

申请日：2004-07-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L29/768

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

公开(公告)号：US20050127466A1

公开(公告)日：2005-06-16

申请号：US10732958

申请日：2003-12-11

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L21/334 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/76 ,  H01L29/00

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US20050104139A1

公开(公告)日：2005-05-19

申请号：US11005659

申请日：2004-12-07

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Edward Nowak

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Edward Nowak

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/7833

摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.

摘要翻译： FET具有T形门。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。 因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。 两层被图案化在一起。 然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。 在另一个实施例中，栅极由单个栅极导体形成。 金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。 蚀刻硅化物以提供凹口。

公开(公告)号：US20090244954A1

公开(公告)日：2009-10-01

申请号：US12055509

申请日：2008-03-26

申请人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

发明人： Ethan H. Cannon ,  Toshiharu Furukawa ,  David Horak ,  Charles W. Koburger, III ,  Jack A. Mandelman

IPC分类号： G11C11/40 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L27/0921 ,  H01L27/1104 ,  H01L29/66181 ,  H03K3/0375

摘要： A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

摘要翻译： 数字逻辑存储结构包括形成在半导体衬底上的交叉耦合的第一和第二互补金属氧化物半导体（CMOS）反相器，所述CMOS反相器包括作为第一存储节点的逻辑补码的第一存储节点和第二存储节点; 第一和第二存储节点都通过开关晶体管选择性地耦合到深沟槽电容器，开关晶体管由耦合到其栅极导体的公共电容开关线控制; 其特征在于，在第一工作模式中，使开关晶体管变得不导通，从而将深沟槽电容器与逆变器存储节点隔离，并且在第二工作模式中，使开关晶体管导通，从而将深沟槽 电容器到其各自的存储节点，从而提供存储节点对单个事件扰乱（SEU）的增加的电阻。

公开(公告)号：US20080117671A1

公开(公告)日：2008-05-22

申请号：US12018915

申请日：2008-01-24

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger

IPC分类号： G11C11/34 ,  G11C7/00

CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

摘要： Structures for memory devices. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

摘要翻译： 存储器件结构。 该结构包括（a）基底; （b）基板上的第一和第二电极区域; 和（c）设置在第一和第二电极区之间的第三电极区。 响应于施加在第一和第三电极区域之间的第一写入电压电位，第三电极区域改变其自身形状，使得响应于随后施加在第一和第三电极区域之间的预先指定的读取电压电势，感测 电流在第一和第三电极区域之间流动。 此外，响应于施加在第二和第三电极区域之间的第二写入电压电位，第三电极区域改变其自身形状，使得响应于施加在第一和第三电极区域之间的预先设定的读取电压电位， 所述感测电流不在第一和第三电极区域之间流动。

公开(公告)号：US20080057671A1

公开(公告)日：2008-03-06

申请号：US11927135

申请日：2007-10-29

申请人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

发明人： Toshiharu Furukawa ,  Robert Gauthier ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/762

CPC分类号： H01L21/76237 ,  H01L21/26533 ,  H01L21/76213 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/1087 ,  H01L29/78

摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该半导体结构包括成形修饰的隔离区，其形成在通常在制造本体CMOS器件的衬底的两个掺杂阱之间的沟槽中。 成形改进的隔离区域可以包括沟槽的加宽的电介质填充部分，其可以可选地包括分隔两个掺杂阱之间的损伤区域的沟槽的附近损伤区域或狭窄的电介质填充部分。 也可以通过在沟槽中的沟槽基底和介电填料之间提供晶格不匹配的层来抑制闩锁。

公开(公告)号：US20080042287A1

公开(公告)日：2008-02-21

申请号：US11924894

申请日：2007-10-26

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L23/52

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。