公开(公告)号：US06966235B1

公开(公告)日：2005-11-22

申请号：US09680286

申请日：2000-10-06

申请人： Eric N. Paton

发明人： Eric N. Paton

IPC分类号： G01D11/24 ,  H01L21/00 ,  H01L21/66

CPC分类号： G01D11/245 ,  H01L21/67253 ,  Y10T29/49771 ,  Y10T29/53022

摘要： Monitoring of parameters using remote sensors, which are attached directly to the product material, allows for non-intrusive entry into the manufacturing area, via the same robotic handling or automated systems used to transport the standard product material. Data is recorded from the sensors, by wireless transmission, or when a signal is impassible, on-board memory will store the data for later downloading.

摘要翻译： 使用直接连接到产品材料的远程传感器对参数的监控允许通过用于运输标准产品材料的相同的机器人处理或自动化系统非侵入性地进入制造区域。 数据通过无线传输从传感器记录下来，或当信号无法通信时，机载存储器将存储数据供以后下载。

公开(公告)号：US06902966B2

公开(公告)日：2005-06-07

申请号：US09983625

申请日：2001-10-25

申请人： Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

发明人： Bin Yu ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Qi Xiang

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/268 ,  H01L21/336 ,  H01L29/417 ,  H01L29/78 ,  H01L21/00

CPC分类号： H01L29/665 ,  H01L21/268

摘要： A method of manufacturing a MOSFET semiconductor device comprises forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate adjacent to the sidewalls spacers; laser thermal annealing to activate the source/drain regions; depositing a layer of nickel over the source/drain regions; and annealing to form a nickel silicide layer disposed on the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The annealing is at temperatures from about 350 to 500° C.

摘要翻译： 一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间形成衬底上的栅电极和栅极氧化物; 在衬底中形成源极/漏极延伸部; 形成第一和第二侧壁间隔物; 在所述衬底内注入掺杂剂以在所述衬底中邻近所述侧壁间隔物形成源/漏区; 激光热退火激活源/漏区; 在源极/漏极区域上沉积镍层; 并退火以形成设置在源/漏区上的硅化镍层。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 退火温度在约350-500℃

公开(公告)号：US06867080B1

公开(公告)日：2005-03-15

申请号：US10460165

申请日：2003-06-13

申请人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

发明人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L21/20 ,  H01L21/268 ,  H01L21/28 ,  H01L21/321 ,  H01L21/8234 ,  H01L21/338 ,  H01L21/331 ,  H01L21/94

CPC分类号： H01L21/28176 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/321 ,  H01L21/823437 ,  Y10S438/926

摘要： A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to “fill in” the spaces between isolated gate electrodes, such that the spacing between the gate electrodes and the dummy structures is the same as the spacing between the densest array of device structures on the substrate surface. Since the surface features (i.e., the gate electrodes and the dummy structures) appear substantially uniform to the LTA laser, the laser radiation is uniformly absorbed by the substrate, and the substrate surface is evenly heated.

摘要翻译： 提供了一种用于消除激光热退火（LTA）期间基板有源区的不均匀加热的方法，这是由于栅电极密度的变化。 实施例包括添加与栅电极同时形成的虚拟结构以“填充”隔离栅电极之间的空间，使得栅电极和虚拟结构之间的间隔与器件结构最密集阵列之间的间隔相同 在基板表面上。 由于表面特征（即，栅电极和虚拟结构）对于LTA激光器而言基本上均匀，激光辐射被基板均匀地吸收，并且基板表面被均匀地加热。

公开(公告)号：US06825115B1

公开(公告)日：2004-11-30

申请号：US10341436

申请日：2003-01-14

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L2144

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665

摘要： Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming metal silicide layers on the substrate surface and gate electrode, forming preamorphized regions under the metal silicide layers in the substrate, ion implanting to form deep source/drain implants overlapping the preamorphized regions and extending deeper into the substrate then the preamorphized regions, and laser thermal annealing to activate the deep source/drain regions.

摘要翻译： 通过在衬底上形成硅化物层并通过激光热退火来激活源极/漏极区域之后形成深源极/漏极注入来避免掺杂失活，特别是Si /硅化物界面。 实施例包括形成源极/漏极延伸部，在衬底表面上形成金属硅化物层和栅电极，在衬底中的金属硅化物层下方形成预变形区域;离子注入，以形成与预变形区域重叠的深源/漏植入物， 衬底然后是前变形区域，激光热退火激活深源/漏区。

公开(公告)号：US06746944B1

公开(公告)日：2004-06-08

申请号：US10341345

申请日：2003-01-14

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/7833

摘要： Semiconductor devices with reduced NiSi/Si interface contact resistance are fabricated by forming preamorphized regions in a substrate at a depth overlapping the subsequently formed NiSi/Si interface, ion implanting impurities to form deep source/drain implants overlapping the preamorphized regions deeper in the substrate and laser thermal annealing to activate the deep source/drain regions. Nickel silicide layers are then formed in a main surface of the substrate and on the gate electrode. Embodiments include forming deep source/drain regions with an activated impurity concentration of 1×1020 to 1×1021 atoms/cm3 at the NiSi/Si interface.

摘要翻译： 具有降低的NiSi / Si界面接触电阻的半导体器件通过在与随后形成的NiSi / Si界面重叠的深度的衬底中形成预变形区域，离子注入杂质以形成与衬底中较深的预变形区域重叠的深源/漏注入; 激光热退火激活深源/漏区。 然后在衬底的主表面和栅电极上形成硅化镍层。 实施例包括在NiSi / Si界面处形成具有1×10 20至1×10 21原子/ cm 3的活化杂质浓度的深源/漏区。

公开(公告)号：US06703648B1

公开(公告)日：2004-03-09

申请号：US10282559

申请日：2002-10-29

申请人： Qi Xiang ,  Eric N. Paton ,  Haihong Wang

发明人： Qi Xiang ,  Eric N. Paton ,  Haihong Wang

IPC分类号： H01L2904

CPC分类号： H01L29/6656 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802 ,  Y10S438/933

摘要： A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

摘要翻译： 应变硅p型MOSFET利用形成在硅锗衬底上的应变硅沟道区。 硅锗区形成在邻近于应变硅沟道区的端部的硅锗层上，并且浅的源极和漏极延伸部被注入到硅锗材料中。 浅源极和漏极延伸部分不延伸到应变硅沟道区域。 通过在硅锗材料而不是在硅中形成源极和漏极延伸，避免了由硅中的增强的扩散速率引起的源极和漏极扩展失真。

公开(公告)号：US06682973B1

公开(公告)日：2004-01-27

申请号：US10147650

申请日：2002-05-16

申请人： Eric N. Paton ,  Qi Xiang ,  Bin Yu

发明人： Eric N. Paton ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L218242

CPC分类号： H01L21/28185 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28291 ,  H01L21/31604 ,  H01L21/31662 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of growing on the silicon substrate an interfacial layer of a silicon-containing dielectric material; and depositing on the interfacial layer a layer comprising at least one high-K dielectric material, in which the interfacial layer is grown by laser excitation of the silicon substrate in the presence of oxygen, nitrous oxide, nitric oxide, ammonia or a mixture of two or more thereof. In one embodiment, the silicon-containing material is silicon dioxide, silicon nitride, silicon oxynitride or a mixture thereof.

摘要翻译： 一种用于制造在硅衬底上具有高K电介质层的半导体器件的方法，包括在硅衬底上生长含硅介电材料的界面层的步骤; 并且在所述界面层上沉积包含至少一种高K电介质材料的层，其中所述界面层通过在氧，一氧化二氮，一氧化氮，氨或两者的混合物的存在下通过硅衬底的激光激发而生长 或更多。 在一个实施方案中，含硅材料是二氧化硅，氮化硅，氮氧化硅或其混合物。

公开(公告)号：US06555439B1

公开(公告)日：2003-04-29

申请号：US10021551

申请日：2001-12-18

申请人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

发明人： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC分类号： H01L2100

CPC分类号： H01L21/324 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28176 ,  H01L21/28211 ,  H01L29/6659

摘要： A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate, forming source/drain extensions in the substrate, and forming first and second sidewall spacers. Dopants are then implanted within the substrate to form amorphitized source/drain regions in the substrate adjacent to the sidewalls spacers. The amorphitized source/drain regions are partially recrystallized, and laser thermal annealing activates the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. Also, the recrystallization reduces the amorphitized source/drain regions by a depth of about 20 to 100 angstroms. A semiconductor device is also disclosed.

摘要翻译： 一种制造MOSFET半导体器件的方法包括在衬底上形成栅电极和在栅电极和衬底之间形成栅极氧化物，在衬底中形成源极/漏极延伸部分，以及形成第一和第二侧壁间隔物。 然后将掺杂剂注入到衬底内以在邻近侧壁间隔物的衬底中形成非晶化的源极/漏极区。 非晶化的源极/漏极区域被部分再结晶，并且激光热退火激活源极/漏极区域。 源极/漏极延伸部和侧壁间隔物与栅电极相邻。 源极/漏极延伸部可以具有约50至300埃的深度，并且源极/漏极区域可以具有约400至1000埃的深度。 此外，重结晶将非晶化的源/漏区减少约20至100埃的深度。 还公开了一种半导体器件。

公开(公告)号：US06551888B1

公开(公告)日：2003-04-22

申请号：US10020496

申请日：2001-12-18

申请人： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

发明人： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

IPC分类号： H01L21336

CPC分类号： H01L21/268 ,  H01L21/2026 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, introducing dopants into the substrate, forming a tuning layer over at least a portion of the substrate, and activating the dopants using laser thermal annealing. The tuning layer causes an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by a portion of substrate not covered by the tuning layer. Additional tuning layers can also be formed over the substrate.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂引入衬底中，在衬底的至少一部分上形成调谐层，并使用激光热退火激活掺杂剂。 与由调谐层未被覆盖的基板的一部分吸收的注量相比，调谐层引起由调谐层下方的基板部分吸收的注量的增加或减少。 也可以在衬底上形成附加的调谐层。