公开(公告)号：US10733046B2

公开(公告)日：2020-08-04

申请号：US15958401

申请日：2018-04-20

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Marco Sforzin ,  Paolo Amato ,  Danilo Caraccio

IPC: H03M13/00 ,  G06F11/10 ,  G06F9/46 ,  G06F13/16

Abstract: Apparatuses and methods related to providing transaction metadata. Providing transaction metadata includes providing an address of data stored in the memory device using an address bus coupled to the memory device and the controller. Providing transaction metadata also includes transferring the data, associated with the address, from the memory device using a data bus coupled to the memory device and the controller. Providing transaction metadata further includes transferring a sideband signal synchronously with the data bus and in conjunction with the address bus using a transaction metadata bus coupled to the memory device and the controller.

公开(公告)号：US20200081853A1

公开(公告)日：2020-03-12

申请号：US16128882

申请日：2018-09-12

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Marco Dallabora ,  Daniele Balluchi ,  Paolo Amato ,  Luca Porzio

IPC: G06F13/16 ,  G06F13/28

Abstract: The present disclosure includes apparatuses and methods related to a hybrid memory system interface. An example computing system includes a processing resource and a storage system coupled to the processing resource via a hybrid interface. The hybrid interface can provide an input/output (I/O) access path to the storage system that supports both block level storage I/O access requests and sub-block level storage I/O access requests.

公开(公告)号：US20190294363A1

公开(公告)日：2019-09-26

申请号：US15927383

申请日：2018-03-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F3/06 ,  G06F12/10

Abstract: An example apparatus comprises a hybrid memory system to couple to a host and a controller coupled to the hybrid memory system. The controller may be configured to cause data associated with a virtual memory location of the host to be selectively transferred to the hybrid memory system responsive to a determination that a main memory of the host experiences threshold amount of resource utilization.

公开(公告)号：US20190266078A1

公开(公告)日：2019-08-29

申请号：US15908545

申请日：2018-02-28

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Graziano Mirichigni ,  Danilo Caraccio

IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06 ,  G11C29/52

Abstract: Devices and techniques for storage class memory status are disclosed herein. A storage portion characteristics data structure is maintained. Here, the data structure includes an array of elements—where each element is sized to contain a reference to a storage portion in a storage class memory storage device, a first pointer to a first element in the array of elements, a second pointer to a second element in the array of elements, and a third pointer to a third element in the array of elements. The data structure includes a direction of pointer motion in which the second pointer precedes the third pointer and the first pointer precedes the second pointer with respect to the direction of pointer motion. A write request is performed to a storage portion reference retrieved from the first element. The first pointer is then advanced.

公开(公告)号：US20190171385A1

公开(公告)日：2019-06-06

申请号：US16201729

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

公开(公告)号：US10083751B1

公开(公告)日：2018-09-25

申请号：US15664014

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0088

Abstract: The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a data pattern in a group of resistance variable memory cells corresponding to a selected managed unit having a first status, updating a status of the selected managed unit from the first status to a second status responsive to performing the write operation, and providing data state synchronization for a subsequent write operation performed on the group by placing all of the variable resistance memory cells of the group in a same state prior to performing the subsequent write operation to store another data pattern in the group of resistance variable memory cells.

公开(公告)号：US09971536B2

公开(公告)日：2018-05-15

申请号：US15431457

申请日：2017-02-13

Applicant: Micron Technology, Inc.

Inventor： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F1/32 ,  G06F12/02 ,  G11C29/52

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F13/1668 ,  G11C29/52 ,  Y02D10/14

Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with multiple memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the multiple memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.

公开(公告)号：US09778875B2

公开(公告)日：2017-10-03

申请号：US14954507

申请日：2015-11-30

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00 ,  G11C13/00

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the apparatus is to manage commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and map portions of a second memory having the attribute enhanced set through a second interface controller. Additional devices are described.

公开(公告)号：US20170160973A1

公开(公告)日：2017-06-08

申请号：US15431457

申请日：2017-02-13

Applicant: Micron Technology, Inc.

Inventor： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F13/1668 ,  G11C29/52 ,  Y02D10/14

Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

公开(公告)号：US09569129B2

公开(公告)日：2017-02-14

申请号：US14967934

申请日：2015-12-14

Applicant: Micron Technology, Inc.

Inventor： Federico Tiziani ,  Giovanni Campardo ,  Massimo Iaculo ,  Claudio Giaccio ,  Manuela Scognamiglio ,  Danilo Caraccio ,  Ornella Vitale ,  Antonino Pollio

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F1/32 ,  G06F12/02 ,  G11C29/52

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F13/1668 ,  G11C29/52 ,  Y02D10/14

Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with a plurality of memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the plurality of the memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.

Abstract translation: 各种实施例公开了一种用于管理存储器件的控制器。 在示例性方法中，信号与主处理器交换，以允许主机处理器作为单个设备与存储器堆叠中的多个存储器件通信，而不管存储器堆栈内的实际数量的存储器件。 一次将功率提供给存储器堆叠中的多个存储器件中的单个存储器件，以降低功耗。 还公开了其它方法，装置和装置。