公开(公告)号：US09064970B2

公开(公告)日：2015-06-23

申请号：US13864794

申请日：2013-04-17

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

公开(公告)号：US20150064871A1

公开(公告)日：2015-03-05

申请号：US14534454

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Hopkins ,  James Matthew ,  Jie Sun ,  Gordon Haller

IPC: H01L21/762 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Abstract translation: 一个实施例包括在半导体中在第一和第二有源区之间形成隔离区，通过去除隔离区的一部分形成第一和第二有源区之间的开口，以及在该开口内形成电介质塞， 在第一和第二有源区之间并且使得电介质塞的一部分延伸到第一和第二有源区的上表面之下。 电介质插塞可以由对于特定的各向同性的去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US20140203344A1

公开(公告)日：2014-07-24

申请号：US13748747

申请日：2013-01-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Hopkins ,  Darwin Franseda Fan ,  Fatma Arzum Simsek-Ege ,  James Brighten ,  Aurelio Giancarlo Mauri ,  Srikant Jayanti

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7887 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/42324 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7889

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract translation: 三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。 在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。 这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。 存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

公开(公告)号：US12250499B2

公开(公告)日：2025-03-11

申请号：US17806888

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： Alyssa Scarbrough ,  John Hopkins ,  Zahra Hosseinimakarem ,  Yi Hu

IPC: H04N7/18 ,  G07C5/08 ,  H04N23/60 ,  H04N23/65

Abstract: In some implementations, a device may receive, from a sensor of a vehicle, sensor data. The device may detect whether an event causing damage to the vehicle has occurred or is expected to occur based on the sensor data being greater than a threshold, wherein the threshold is based on an on-off status of the vehicle and a sensor type. The device may activate, based on whether the event has occurred or is expected to occur, a camera of the vehicle to capture video data of a scene associated with the vehicle. The device may transmit, to a server, an indication that indicates the event and the video data.

公开(公告)号：US20230380172A1

公开(公告)日：2023-11-23

申请号：US17748924

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： John Hopkins ,  Jordan D. Greenlee ,  Daniel Billingsley ,  Alyssa N. Scarbrough

IPC: H01L27/11573 ,  H01L27/11529

CPC classification number: H01L27/11573 ,  H01L27/11529

Abstract: Methods, systems, and devices for a barrier structure for preventing removal of, such as etching to, control circuitry are described. A memory device may include control circuitry over a substrate and for accessing a memory array and contact regions configured to couple with the control circuitry. The memory device may include barrier regions between respective contact regions that includes a barrier material. The memory device may include a stack of layers over the barrier region and the contact regions that is associated with the memory array, and the barrier material may prevent a removal (e.g., an etch) through the stack of layers and at least partially between contact regions from extending to the control circuitry.

公开(公告)号：US20230117100A1

公开(公告)日：2023-04-20

申请号：US18083991

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lise M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L23/522 ,  H01L21/02 ,  H10B51/20 ,  H01L21/67

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US11532638B2

公开(公告)日：2022-12-20

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11597 ,  H01L21/02 ,  H01L21/67 ,  G11C16/04

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20220310524A1

公开(公告)日：2022-09-29

申请号：US17216210

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett Allen McTeer ,  John Hopkins ,  David Ross Economy

IPC: H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first dielectric material; a second dielectric material separated from the first dielectric material; a memory cell string including a pillar extending through the first and second dielectric materials, the pillar including a portion between the first and second dielectric materials; an additional dielectric material contacting the portion of the pillar; a conductive material contacting the additional dielectric material; and a tungsten structure including a portion of tungsten contacting the conductive material, wherein a majority of the portion of tungsten is beta-phase tungsten.

公开(公告)号：US10833099B2

公开(公告)日：2020-11-10

申请号：US16419736

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L21/02 ,  H01L27/11582 ,  G11C16/14 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11529 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

公开(公告)号：US20190214399A1

公开(公告)日：2019-07-11

申请号：US16237287

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

IPC: H01L27/11556 ,  H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11524 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.