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51.发明授权公开(公告)号：US12007838B2
公开(公告)日：2024-06-11
申请号：US17877637
申请日：2022-07-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vamsi Pavan Rayaprolu , Dung Viet Nguyen , Zixiang Loh , Sampath K Ratnam , Patrick R. Khayat , Thomas Herbert Lentz
CPC classification number: G06F11/1044
Abstract: A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.
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公开(公告)号：US11995320B2
公开(公告)日：2024-05-28
申请号：US17824562
申请日：2022-05-25
Applicant: Micron Technology, Inc.
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0653 , G06F3/0679
Abstract: A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.
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公开(公告)号：US11994936B2
公开(公告)日：2024-05-28
申请号：US17897910
申请日：2022-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jay Sarkar , Ipsita Ghosh , Vamsi Pavan Rayaprolu
IPC: G06F11/07
CPC classification number: G06F11/0784 , G06F11/0757 , G06F11/0787
Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.
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公开(公告)号：US11941277B2
公开(公告)日：2024-03-26
申请号：US18118082
申请日：2023-03-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shane Nowell , Michael Sheperek , Larry J. Koudele , Vamsi Pavan Rayaprolu
CPC classification number: G06F3/064 , G06F3/0619 , G06F3/0629 , G06F3/0653 , G06F3/0659 , G06F3/0679
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.
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公开(公告)号：US11907536B2
公开(公告)日：2024-02-20
申请号：US18093069
申请日：2023-01-04
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Vamsi Pavan Rayaprolu , Kishore K. Muchherla
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0646 , G06F3/0679
Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.
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Patent Agency Ranking
公开(公告)号：US20240053893A1
公开(公告)日：2024-02-15
申请号：US17884327
申请日：2022-08-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jay Sarkar , Vamsi Pavan Rayaprolu , Ipsita Ghosh
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0679 , G06F3/0629
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.
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公开(公告)号：US20240021258A1
公开(公告)日：2024-01-18
申请号：US18373741
申请日：2023-09-27
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Michael Sheperek , Chris Smitchger
CPC classification number: G11C29/021 , G11C29/12005 , G11C29/50004 , G11C29/44 , G11C2207/2254
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric value satisfies a first threshold criterion, obtaining, from a neural network, a value of a voltage distribution metric associated with the page; and upon determining that the voltage distribution metric value satisfies a second threshold criterion, performing a media management operation with respect to a block associated with the page, wherein the media management operation comprises writing data stored at the block to a new block.
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公开(公告)号：US11868639B2
公开(公告)日：2024-01-09
申请号：US17350866
申请日：2021-06-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
CPC classification number: G06F3/0647 , G06F3/0619 , G06F3/0673 , G06F11/1068 , G06F11/1402 , G11C29/52
Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
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公开(公告)号：US20230393938A1
公开(公告)日：2023-12-07
申请号：US17859468
申请日：2022-07-07
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Patrick Khayat , Sampath Ratnam , Kishore Kumar Muchherla , Jiangang Wu , James Fitzpatrick
CPC classification number: G06F11/1068 , G06F11/0772 , G06F11/076
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.
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公开(公告)号：US20230393736A1
公开(公告)日：2023-12-07
申请号：US17830166
申请日：2022-06-01
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Patrick R. Khayat , James Fitzpatrick , Kishore Kumar Muchherla , Sivagnanam Parthasarathy , Ashutosh Malshe
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0679 , G06F3/0655
Abstract: One of a plurality of compaction strategies to be performed on the memory device based on at least one characteristic of a memory device is identified. Each of the plurality of compaction strategies is to program host data from at least one single-level cell (SLC) of the memory device to at least one quad-level cell (QLC) of the memory device. One or more host data from a host system is received. A compaction operation on the one or more host data using the one of the plurality of compaction strategies is performed.
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