公开(公告)号：US12256546B2

公开(公告)日：2025-03-18

申请号：US18386346

申请日：2023-11-02

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Andrew Li ,  Haoyu Li ,  Matthew J. King ,  Wei Yeeng Ng ,  Yongjun Jeff Hu

IPC: H10B43/00 ,  H01L21/283 ,  H01L21/306 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240373636A1

公开(公告)日：2024-11-07

申请号：US18621738

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David H. Wells ,  Yiping Wang ,  Mojtaba Asadirad ,  Harsh Narendrakumar Jain

IPC: H10B43/27 ,  H10B41/27

Abstract: A method of forming a microelectronic device comprises forming a preliminary stack structure over a source structure. The preliminary stack structure comprises a vertically alternating sequence of insulative material and sacrificial material arranged in preliminary tiers. The method comprises forming a staircase structure having steps comprising edges of at least some of the preliminary tiers of the preliminary stack structure, forming implant regions within exposed portions of the sacrificial material at the steps of the staircase structure, forming openings extending through the preliminary stack structure to the source structure and within a horizontal area of the staircase structure, replacing portions of the sacrificial material with conductive structures, forming strapping structures comprising conductive material, at locations vacated by the implant regions, laterally adjacent to the conductive structures at the steps of the staircase structure, and forming conductive contacts within the openings. Additional methods and microelectronic devices are also described.

公开(公告)号：US20240315027A1

公开(公告)日：2024-09-19

申请号：US18602313

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Collin Howder ,  Matthew J. King

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Memory circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises laterally-spaced memory blocks. The memory blocks individually comprise sub-blocks in an upper portion thereof. Strings of memory cells are included and that comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A conductive-material tier is included and that comprises conductive material in the upper portions. The conductive material extends downwardly from the conductive-material tier to below the conductive-material tier. Sub-block trenches in the upper portions are individually between immediately-laterally-adjacent of the sub-blocks and extend through the conductive-material tier. Select gates of select-gate transistors are in individual of the sub-blocks operatively alongside channel material of the select-gate transistors. The select gates comprise the conductive material of the conductive-material tier and the conductive material extending downwardly from the conductive-material tier to below the conductive-material tier alongside the channel material of the select-gate transistors. Methods are also disclosed.

公开(公告)号：US12063778B2

公开(公告)日：2024-08-13

申请号：US17661781

申请日：2022-05-03

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Kunal Shrotri ,  Matthew J. King

IPC: H10B41/27 ,  H01L21/768 ,  H10B41/10 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H01L21/76801 ,  H10B41/10 ,  H10B41/35 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.

公开(公告)号：US20240237352A1

公开(公告)日：2024-07-11

申请号：US18581667

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  John D. Hopkins ,  Matthew J. King ,  Roger W. Lindsay ,  Kevin Y. Titus

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/27

Abstract: A microelectronic device includes a pair of stack structures. The pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. The lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A source region is vertically interposed between the lower stack structure and the upper stack structure. A first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. A second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.

公开(公告)号：US20240081076A1

公开(公告)日：2024-03-07

申请号：US17929911

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  Matthew J. King ,  Jiewei Chen ,  Yi Hu

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures adjacent to a source, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprising a channel material extending vertically through the stack. The electronic device comprises an additional stack adjacent to the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, pillars extending through the additional stack and adjacent to the strings of memory cells, conductive contacts adjacent to the pillars, and isolation structures laterally intervening between neighboring pillars. The isolation structures exhibit a weave pattern, and portions of the isolation structures are laterally adjacent to and physically contact the conductive contacts. Related memory devices, systems, and methods are also described.

公开(公告)号：US20240064982A1

公开(公告)日：2024-02-22

申请号：US18386346

申请日：2023-11-02

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Andrew Li ,  Haoyu Li ,  Matthew J. King ,  Wei Yeeng Ng ,  Yongjun Jeff Hu

IPC: H10B43/27 ,  H01L21/283 ,  H01L21/306 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/283 ,  H01L21/30608 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11641741B2

公开(公告)日：2023-05-02

申请号：US17016039

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Kaiming Luo ,  Sarfraz Qureshi ,  Md Zakir Ullah ,  Jessica Jing Wen Low ,  Harsh Narendrakumar Jain ,  Kok Siak Tang ,  Indra V. Chary ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11568

Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of slit structures extends through the stack structure and divides the stack structure into a series of blocks. In a progressed portion of the series of blocks, each block comprises an array of pillars extending through the stack structure of the block. Also, each block—in the progressed portion—has a different block width than a block width of a neighboring block of the progressed portion of the series of blocks. At least one pillar, of the pillars of the array of pillars in the progressed portion, exhibits bending. Related methods and electronic systems are also disclosed.

公开(公告)号：US20230063178A1

公开(公告)日：2023-03-02

申请号：US17564633

申请日：2021-12-29

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Matthew J. King ,  Jason Reece ,  Michael J. Gossman ,  Shruthi Kumara Vadivel ,  Martin J. Barclay ,  Lifang Xu ,  Joel D. Peterson ,  Matthew Park ,  Adam L. Olson ,  David A. Kewley ,  Xiaosong Zhang ,  Justin B. Dorhout ,  Zhen Feng Yow ,  Kah Sing Chooi ,  Tien Minh Quan Tran ,  Biow Hiem Ong

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A microelectronic device includes a stack structure including a vertically alternating sequence of conductive structures and insulating structures arranged in tiers, a dielectric-filled opening vertically extending into the stack structure and defined between two internal sidewalls of the stack structure, a stadium structure within the stack structure and comprising steps defined by horizontal ends of at least some of the tiers, a first ledge extending upward from a first uppermost step of the steps of the stadium structure and interfacing with a first internal sidewall of the two internal sidewalls of the stack structure, and a second ledge extending upward from a second, opposite uppermost step of the steps of the stadium structure and interfacing with a second, opposite internal sidewall of the two internal sidewalls.

公开(公告)号：US20230041326A1

公开(公告)日：2023-02-09

申请号：US17397603

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Albert Fayrushin ,  Matthew J. King ,  Madison D. Drake

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/78 ,  H01L29/66

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.