公开(公告)号：US4894691A

公开(公告)日：1990-01-16

申请号：US42330

申请日：1987-04-24

申请人： Yuichi Matsui

发明人： Yuichi Matsui

IPC分类号： H01L29/812 ,  H01L21/203 ,  H01L21/285 ,  H01L21/338 ,  H01L29/15 ,  H01L29/45 ,  H01L29/778

CPC分类号： H01L29/452 ,  H01L21/28575 ,  H01L29/155 ,  H01L29/7783

摘要： A compound semiconductor device having a channel layer which is made of periodically laminated structure of thin-film layers of compound semiconductor substantially being different from each other. The difference of energy between the conduction band and the valence band of compound semiconductor thin-film layers of one side is less than that of the other side thin-film layers, moreover the electron mobility in low electric field application in the thin-film layers of compound semiconductor of one side is greater than that of the other side thin-film layers, besides the electron mobility in high electric field application in the thin-film layers of compound semiconductor of one side is less than that of the other side thin-film layers, and/or the impact ionization of valence electron generated in high electric field application takes place earlier than the thin-film layers of compound semiconductor of the other side. While conduction electron preferentially flows through the thin-film layers of compound semiconductor of one side in low electric field application, and conversely, while conduction electron having substantial energy intensified by acceleration preferentially flows through other side thin-film layers in high electric field application.

摘要翻译： 一种具有沟道层的化合物半导体器件，该沟道层由化合物半导体的薄膜层的周期性层叠结构构成，其基本上彼此不同。 一侧化合物半导体薄膜层的导带与价带之间的能量差小于另一侧薄膜层的能量差，此外，薄膜层中低电场中的电子迁移率 的化合物半导体的一面比另一方薄膜层的化学半导体的电子迁移率小，另外侧面化合物半导体的薄膜层的电场迁移率小于另一侧薄膜层的电场迁移率， 和/或在高电场施加中产生的价电子的撞击电离比另一侧的化合物半导体的薄膜层更早发生。 虽然传导电子优先在低电场施加中流过一侧的化合物半导体的薄膜层，相反地，在高电场应用中，通过加速强化的实质能量的传导电子优先流过另一侧薄膜层。

公开(公告)号：US08106441B2

公开(公告)日：2012-01-31

申请号：US12861407

申请日：2010-08-23

申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/06

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

摘要翻译： DRAM的存储单元电容器（C3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同层（M3）的金属布线作为其电极，从而能够减少 工艺成本 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

公开(公告)号：US20100314676A1

公开(公告)日：2010-12-16

申请号：US12861407

申请日：2010-08-23

申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

摘要翻译： DRAM的存储单元电容器（C3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同层（M3）的金属布线作为其电极，从而能够减少 工艺成本 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

公开(公告)号：US07804118B2

公开(公告)日：2010-09-28

申请号：US12635181

申请日：2009-12-10

申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L29/78

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

公开(公告)号：US20080035979A1

公开(公告)日：2008-02-14

申请号：US11878475

申请日：2007-07-25

申请人： Yuichi Matsui ,  Masahiko Hiratani

发明人： Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L21/022 ,  C23C16/18 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31604 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75 ,  H01L28/90

摘要： The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

摘要翻译： 本发明涉及半导体电容器存储器件的电容器的结构，特别是五氧化二铌。 由于五氧化二铌具有600℃以下的低结晶温度，所以五氧化二铌可以通过热处理抑制底电极和阻挡金属的氧化。 然而，根据低温热处理，从CVD源引入到膜中的碳不易氧化或除去。 因此，出现漏电流增加的问题。 作为电容器的绝缘膜，使用由五氧化二铌膜和五氧化钽膜构成的层叠膜或由五氧化二铌膜构成的层叠膜。 通过使用五氧化二铌膜，可以使电容器的介电常数高，可以降低结晶温度。 通过电介质膜的多级形成，可以降低泄漏电流。

公开(公告)号：US20070257295A1

公开(公告)日：2007-11-08

申请号：US11713591

申请日：2007-03-05

申请人： Hiroshi Miki ,  Yuichi Matsui

发明人： Hiroshi Miki ,  Yuichi Matsui

IPC分类号： H01L29/94

CPC分类号： H01L28/65 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： A capacitance of a capacitor including a metal electrode is increased by using a dielectric film having a high dielectric constant. A band gap is reduced as the dielectric constant of a material is increased. In a dielectric having the dielectric constant of 50 or more such as strontium titanate, the high dielectric constant is ensured due to the crystallization but the side effect of the increased leakage current occurs. Since the replacement of the material requires the significant change of the manufacturing apparatus or the manufacturing process, the manufacturing cost is increased.Hafnium oxide is not replaced with the other materials, but the dielectric constant of hafnium oxide is improved to increase the capacitance. An element having a large ion radius such as yttrium is added in a small amount to increase the dielectric constant of hafnium while an amorphous state is maintained. The capacitor process where the amorphous state is maintained is applied to produce the DRAM at low cost.

摘要翻译： 通过使用具有高介电常数的电介质膜来增加包括金属电极的电容器的电容。 当材料的介电常数增加时，带隙减小。 介电常数为50以上的电介质，例如钛酸锶，由于结晶化，保证了高的介电常数，而且发生漏电流增加的副作用。 由于更换材料需要制造装置或制造工艺的显着变化，所以制造成本增加。 氧化铪不被其他材料替代，但是改善了氧化铪的介电常数以增加电容。 少量添加离子半径大的元素如钇，以增加铪的介电常数，同时保持非晶状态。 施加保持非晶态的电容器工艺以低成本制造DRAM。

公开(公告)号：US20050001212A1

公开(公告)日：2005-01-06

申请号：US10829300

申请日：2004-04-22

申请人： Yuichi Matsui

发明人： Yuichi Matsui

IPC分类号： H01L21/316 ,  H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L31/0376

CPC分类号： H01L28/56 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02356 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/65 ,  H01L28/90

摘要： A capacitor uses niobium pentoxide in the manufacture of a semiconductor device. The niobium pentoxide has a low crystallization temperature of 600° C. that provides control over the oxidation of the bottom electrode during heat-treatment. A dielectric constituent present as an amorphous oxide along the grain boundaries of polycrystalline niobium pentoxide is used for a capacitor insulator., thereby providing a method to decrease the leakage current along the grain boundary of niobium pentoxide and to realize a high dielectric constant and low-temperature crystallization.

摘要翻译： 电容器使用五氧化二铌制造半导体器件。 五氧化二铌具有600℃的低结晶温度，其在热处理期间提供对底部电极的氧化的控制。 作为电容绝缘体，使用沿着多晶铌五氧化物的晶界作为非晶形氧化物存在的电介质成分，从而提供减少沿着五氧化二铌的晶界的漏电流并实现高介电常数和低介电常数的方法， 温度结晶。

公开(公告)号：US06720603B2

公开(公告)日：2004-04-13

申请号：US10321614

申请日：2002-12-18

申请人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

发明人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

IPC分类号： H01L27108

CPC分类号： H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/91

摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

摘要翻译： 形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。 在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。 在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

公开(公告)号：US5086014A

公开(公告)日：1992-02-04

申请号：US584110

申请日：1990-09-18

申请人： Koichi Miyata ,  Kazuo Kumagai ,  Koji Kobashi ,  Yuichi Matsui ,  Akimitsu Nakaue

发明人： Koichi Miyata ,  Kazuo Kumagai ,  Koji Kobashi ,  Yuichi Matsui ,  Akimitsu Nakaue

IPC分类号： H01L21/205 ,  H01L21/04 ,  H01L21/20 ,  H01L21/285 ,  H01L29/16 ,  H01L29/45 ,  H01L29/47 ,  H01L29/862 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L21/02381 ,  H01L21/02527 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28537 ,  H01L29/1602 ,  H01L29/45 ,  H01L29/6603 ,  H01L29/862 ,  Y10S148/14

摘要： A schottky diode manufacturing process employing diamond film comprises forming a B-doped p-type polycrystalline diamond film on a low-resistance p-type Si substrate by CVD using a source gas consisting of CH.sub.4, H.sub.2 and B.sub.2 H.sub.6, forming an ohmic contact on the back of the p-type Si substrate, and forming a metal electrode of Al, Pt Au, Ti or W on the B-doped p-type polycrystalline diamond film. The B/C concentration ratio of the source gas is greater than 0.01 ppm and less than 20 ppm.

摘要翻译： 使用金刚石膜的肖特基二极管制造方法包括通过使用由CH 4，H 2和B 2 H 6组成的源气体的CVD在低电阻p型Si衬底上形成B掺杂的p型多晶金刚石膜，在其上形成欧姆接触 并且在B掺杂的p型多晶金刚石膜上形成Al，Pt Au，Ti或W的金属电极。 源气体的B / C浓度比大于0.01ppm且小于20ppm。