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    MOS technology power device with low output resistance and low capacitance, and related manufacturing process
    51.
    发明授权
    MOS technology power device with low output resistance and low capacitance, and related manufacturing process 有权
    MOS技术功率器件具有低输出电阻和低电容，以及相关的制造工艺

    公开(公告)号：US06228719B1

    公开(公告)日：2001-05-08

    申请号：US09235067

    申请日：1999-01-21

    申请人： Ferruccio Frisina ,  Giuseppe Ferla ,  Salvatore Rinaudo

    发明人： Ferruccio Frisina ,  Giuseppe Ferla ,  Salvatore Rinaudo

    IPC分类号： H01L21336

    CPC分类号： H01L29/7802 ,  H01L29/0847 ,  H01L29/66712

    摘要： A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

    摘要翻译： MOS门控功率器件包括多个基本功能单元，每个基本功能单元包括形成在具有第一电阻率值的第二导电类型的半导体材料层中的第一导电类型的体区。 在每个体区下方提供具有高于第一电阻率值的第二电阻率值的第二导电类型的相应轻掺杂区。

    High speed MOS-technology power device integrated structure, and related manufacturing process
    52.
    发明授权
    High speed MOS-technology power device integrated structure, and related manufacturing process 失效
    高速MOS技术功率器件集成结构及相关制造工艺

    公开(公告)号：US5933734A

    公开(公告)日：1999-08-03

    申请号：US813009

    申请日：1997-03-04

    申请人： Giuseppe Ferla ,  Ferruccio Frisina

    发明人： Giuseppe Ferla ,  Ferruccio Frisina

    IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78 ,  H01L21/8236

    CPC分类号： H01L29/7802 ,  H01L29/4933 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/4238 ,  H01L2924/0002

    摘要： A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the insulated gate layer is lowered.

    摘要翻译： 高速MOS技术功率器件集成结构包括形成在第一导电类型的轻掺杂半导体层中的多个基本功能单元，所述基本功能单元包括由导电绝缘栅层覆盖的第二导电类型的沟道区 包括多晶硅层; 导电绝缘栅极层还包括叠加在多晶硅层上的高导电层，并且具有比多晶硅层的电阻率低得多的电阻率，使得由多晶硅层引入的电阻被由高导电层引入的电阻分流 并且绝缘栅极层的整体电阻率降低。

    Low gate resistance high-speed MOS-technology integrated structure
    54.
    发明授权
    Low gate resistance high-speed MOS-technology integrated structure 失效
    低栅极电阻高速MOS技术集成结构

    公开(公告)号：US5883412A

    公开(公告)日：1999-03-16

    申请号：US502240

    申请日：1995-07-13

    申请人： Giuseppe Ferla ,  Ferruccio Frisina

    发明人： Giuseppe Ferla ,  Ferruccio Frisina

    IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62

    CPC分类号： H01L29/7802 ,  H01L29/4933 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/4238 ,  H01L2924/0002

    摘要： A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the conductive insulated gate layer is lowered.

    摘要翻译： 高速MOS技术功率器件集成结构包括形成在第一导电类型的轻掺杂半导体层中的多个基本功能单元，所述基本功能单元包括由导电绝缘栅层覆盖的第二导电类型的沟道区 包括多晶硅层; 导电绝缘栅极层还包括叠加在多晶硅层上的高导电层，并且具有比多晶硅层的电阻率低得多的电阻率，使得由多晶硅层引入的电阻被由高导电层引入的电阻分流 并且导电绝缘栅极层的整体电阻率降低。

    Power device integrated structure with low saturation voltage
    57.
    发明授权
    Power device integrated structure with low saturation voltage 失效
    功率器件集成结构，饱和电压低

    公开(公告)号：US5631483A

    公开(公告)日：1997-05-20

    申请号：US509881

    申请日：1995-08-01

    申请人： Giuseppe Ferla ,  Ferruccio Frisina

    发明人： Giuseppe Ferla ,  Ferruccio Frisina

    IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/76

    CPC分类号： H01L29/7395

    摘要： A power device integrated structure includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type superimposed over the substrate, a plurality of first doped regions of the first conductivity type formed in the semiconductor layer, and a respective plurality of second doped regions of the second conductivity type formed inside the first doped regions. The power device includes: a power MOSFET having a fisrt electrode region formed by the second doped regions and a second electrode region formed by the semiconductor layer; a first bipolar junction transistor having an emitter, a base and a collector respectively formed by the substrate, the semiconductor layer and the first doped regions; and a second bipolar junction transistor having an emitter, a base and a collector respectively formed by the second doped regions, the first doped regions and the semiconductor layer. The doping profiles of the semiconductor substrate, the semiconductor layer, the first doped regions and the second doped regions are such that the first and second bipolar junction transistors have respective first and second common base current gains sufficiently high to cause the bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate into the semiconductor layer and from the second doped regions, through the first doped regions, into the semiconductor layer to modulate the conductivity of the second electrode of the power MOSFET; the fast and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on.

    摘要翻译： 功率器件集成结构包括第一导电类型的半导体衬底，叠加在衬底上的第二导电类型的半导体层，形成在半导体层中的多个第一导电类型的第一掺杂区和多个 形成在第一掺杂区域内的第二导电类型的第二掺杂区域。 功率器件包括：功率MOSFET，具有由第二掺杂区域形成的电极区域和由半导体层形成的第二电极区域; 第一双极结型晶体管，具有分别由衬底，半导体层和第一掺杂区域形成的发射极，基极和集电极; 以及分别由第二掺杂区域，第一掺杂区域和半导体层分别形成的发射极，基极和集电极的第二双极结型晶体管。 半导体衬底，半导体层，第一掺杂区域和第二掺杂区域的掺杂分布使得第一和第二双极结型晶体管具有足够高的相应的第一和第二公共基极电流增益，以使双极结型晶体管为 偏置在高注入区域中，使得载流子从衬底注入到半导体层中，并且从第二掺杂区域通过第一掺杂区域注入到半导体层中，以调制功率MOSFET的第二电极的导电性; 快速和第二共同基极电流增益相加均小于单位，以防止寄生晶闸管触发。

    Method of making electronic power device realized by a series of elementary semiconductor components connected in parallel
    58.
    发明授权
    Method of making electronic power device realized by a series of elementary semiconductor components connected in parallel 失效
    通过并联连接的一系列基本半导体元件实现的制造电子设备的方法

    公开(公告)号：US5397745A

    公开(公告)日：1995-03-14

    申请号：US77375

    申请日：1993-06-17

    申请人： Giuseppe Ferla ,  Cesare Ronsisvalle ,  Pier E. Zani

    发明人： Giuseppe Ferla ,  Cesare Ronsisvalle ,  Pier E. Zani

    IPC分类号： H01L25/07 ,  H01L23/051 ,  H01L23/50 ,  H01L23/525 ,  H01L25/18 ,  H01L21/60

    CPC分类号： H01L23/051 ,  H01L23/50 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/13055

    摘要： Plural modular elementary semiconductor power components are respectively contained within plural semiconductor chip regions of a same semiconductor slice. A metallic layer covers a first surface of the semiconductor slice and is commonly connected to anode electrodes of the plural elementary power components. Plural space apart quadrangular metallic layer regions respectively cover the plural semiconductor chip regions on a second surface of the semiconductor slice and are respectively connected to cathode electrodes of the plural elementary power components. Plural first metallic tracks are spaced apart from and surround the respective plural metallic layer regions on the second surface of the semiconductor slice. Each respective first metallic track is connected to a control electrode of the elementary power component contained within the semiconductor chip regions surrounded by the respective first metallic track. Plural second metallic tracks extend spaced apart from and between the plural first metallic tracks to form a lattice configuration on the second surface of the semiconductor slice. Plural fuse elements, for selectively isolating defective elementary power components, are located on the second surface of the semiconductor slice and connect the first and second metallic tracks.

    摘要翻译： 多个模块化基本半导体功率元件分别包含在相同半导体片的多个半导体芯片区域内。 金属层覆盖半导体片的第一表面，并且通常连接到多个基本功率元件的阳极电极。 多个隔开的四边形金属层区域分别覆盖半导体片的第二表面上的多个半导体芯片区域，并且分别连接到多个基本功率部件的阴极电极。 多个第一金属轨道与半导体片的第二表面上的相应的多个金属层区域间隔开并围绕。 每个相应的第一金属轨道连接到包含在由相应的第一金属轨道包围的半导体芯片区域内的基本功率分量的控制电极。 多个第二金属轨道与多个第一金属轨道间隔开并且在多个第一金属轨道之间延伸，以在半导体片的第二表面上形成晶格构型。 用于选择性地隔离有缺陷的基本功率元件的多个熔丝元件位于半导体片的第二表面上，并连接第一和第二金属轨道。

    Method for the manufacture of semiconductor devices with planar junctions having a variable charge concentration and a very high breakdown voltage
    59.
    发明授权
    Method for the manufacture of semiconductor devices with planar junctions having a variable charge concentration and a very high breakdown voltage 失效
    用于制造具有可变电荷浓度和非常高的击穿电压的具有平面结的半导体器件的方法

    公开(公告)号：US4667393A

    公开(公告)日：1987-05-26

    申请号：US768028

    申请日：1985-08-21

    申请人： Giuseppe Ferla ,  Salvatore Musumeci

    发明人： Giuseppe Ferla ,  Salvatore Musumeci

    IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

    CPC分类号： H01L29/0615 ,  H01L29/1004 ,  H01L29/36 ,  Y10S148/01 ,  Y10S438/965

    摘要： The invention relates to a method for the manufacture of high voltage semiconductor devices with at least one planar junction with a variable charge concentration.The method consists in doping with impurities of a same type, in a region of monocrystalline semiconductor material, a first zone, and then a second zone which comprises the first, and so on, and in carrying out a subsequent heat treatment so as to provide a planar junction with a stepped profile and a concentration of impurities which decreases from the center to the periphery in a predetemined range. In this way the intensity of the surface electric field, when the junction is reverse biased, is reduced as a result of which it is possible to provide planar junctions having very high breakdown voltages of some thousands of volts.

    摘要翻译： 本发明涉及制造具有至少一个具有可变电荷浓度的平面结的高电压半导体器件的方法。 该方法包括掺杂相同类型的杂质，在单晶半导体材料的区域中，第一区域，然后是第二区域，该第二区域包括第一等等，并且进行随后的热处理，从而提供 具有阶梯轮廓的平面结和在预定范围内从中心到外围减少的杂质浓度。 以这种方式，当结被反向偏置时，表面电场的强度被减小，由此可以提供具有几千伏特的非常高的击穿电压的平面结。