公开(公告)号：US20090130834A1

公开(公告)日：2009-05-21

申请号：US12188482

申请日：2008-08-08

申请人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

发明人： Young-Jin Noh ,  Bon-Young Koo ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Chul-Sung Kim ,  Sung-Kweon Baek ,  Jin-Hwa Heo

IPC分类号： H01L21/4763 ,  H01L21/469

CPC分类号： H01L29/42324 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/3145 ,  H01L21/31662

摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.

摘要翻译： 形成绝缘膜的方法包括在基板上形成绝缘膜。 使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。 在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。 注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

公开(公告)号：US20080070368A1

公开(公告)日：2008-03-20

申请号：US11902209

申请日：2007-09-20

申请人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yl

发明人： Hong-Suk Kim ,  Si-Young Choi ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Seung-Jae Baik ,  Sun-Jung Kim ,  Kwang-Min Park ,  In-Sun Yl

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/792 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28282 ,  H01L21/3185 ,  H01L29/4234 ,  H01L29/518 ,  H01L29/7923

摘要： In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

摘要翻译： 在制造非易失性存储器件的方法中，隧道绝缘层可以形成在衬底的沟道区上。 可以在隧道绝缘层上形成包括氮化硅的电荷俘获层，以从沟道区捕获电子。 可以使用包括氮气的第一气体和包括氧的第二气体来进行热处理，以去除电荷捕获层中的缺陷位点并致密化电荷捕获层。 可以在热处理的电荷俘获层上形成阻挡层，然后可以在阻挡层上形成导电层。 阻挡层，导电层，热处理电荷捕获层和隧道绝缘层可以被图案化以在沟道区上形成栅极结构。 因此，可以提高包括门结构的非易失性存储器件的数据保持性能和/或可靠性。

公开(公告)号：US20070001209A1

公开(公告)日：2007-01-04

申请号：US11516707

申请日：2006-09-07

申请人： Kyoung-Seok Kim ,  Ki-Hyun Hwang ,  Hyo-Jung Kim ,  Hyeon-Deok Lee ,  Seok-Woo Nam

发明人： Kyoung-Seok Kim ,  Ki-Hyun Hwang ,  Hyo-Jung Kim ,  Hyeon-Deok Lee ,  Seok-Woo Nam

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L28/84 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/90

摘要： In a storage electrode of a semiconductor device, and a method of forming the same, the storage electrode includes an outer cylinder including a first outer cylindrical portion having a first outer diameter, and a second outer cylindrical portion that is formed on the first outer cylindrical portion and having a second outer diameter, which is less than the first outer diameter, the first and second outer cylindrical portions having substantially equal inner diameters, and an inner cylinder formed on inner surfaces of the outer cylinder.

摘要翻译： 在半导体器件的存储电极及其形成方法中，所述存储电极包括：外筒，所述外筒包括具有第一外径的第一外筒部和形成在所述第一外筒上的第二外筒部; 部分具有小于第一外径的第二外径，第一和第二外筒部具有基本相等的内径，以及形成在外筒内表面上的内筒。

公开(公告)号：US20050170603A1

公开(公告)日：2005-08-04

申请号：US11024981

申请日：2004-12-30

申请人： Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

发明人： Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/20

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/91

摘要： A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the electrode plugs, forming recesses in portions of the mold oxide film and the etching stopper film, the recesses exposing the electrode plugs, forming storage node electrodes in the recesses, filling the recesses in which the storage node electrodes are formed with an artificial oxide film, planarizing the storage node electrodes and the artificial oxide film so that the storage node electrodes are separated from one another, and selectively removing the mold oxide film and the artificial oxide film using a diluted hydrofluoric acid solution containing substantially no ammonium bifluoride.

摘要翻译： 一种用于形成用于半导体器件的电容器的方法，所述半导体器件具有由绝缘膜包围并连接到下面的接触焊盘的电极塞，包括在所述绝缘膜和所述电极插塞上顺序地形成蚀刻停止膜和模制氧化物膜， 在模具氧化膜和蚀刻停止膜的部分中，露出电极塞的凹部，在凹部中形成存储节点电极，用存储节点电极填充形成有人造氧化膜的凹部，使存储节点电极平坦化 和人造氧化物膜，使得储存节点电极彼此分离，并且使用基本上不含氟化二氢铵的稀释的氢氟酸溶液选择性地除去模制氧化物膜和人造氧化物膜。

公开(公告)号：US06329266B1

公开(公告)日：2001-12-11

申请号：US09323500

申请日：1999-06-01

申请人： Ki-Hyun Hwang ,  Seok-Woo Nam

发明人： Ki-Hyun Hwang ,  Seok-Woo Nam

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method of forming an isolation trench for an integrated circuit device includes forming a trench mask layer on a surface of a semiconductor substrate wherein a portion of the semiconductor substrate is exposed through the trench mask layer. An isolation trench is formed in the exposed portion of the semiconductor substrate, and a nitride liner is formed on surfaces of the isolation trench. A trench isolation layer is formed on the nitride liner wherein the trench isolation layer fills the trench, and the trench mask layer is damaged. The damaged trench mask layer is stripped so that the surface of the semiconductor substrate is exposed.

摘要翻译： 形成用于集成电路器件的隔离沟槽的方法包括在半导体衬底的表面上形成沟槽掩模层，其中半导体衬底的一部分通过沟槽掩模层露出。 在半导体衬底的暴露部分中形成隔离沟槽，并且在隔离沟槽的表面上形成氮化物衬垫。 在氮化物衬垫上形成沟槽隔离层，其中沟槽隔离层填充沟槽，并且沟槽掩模层被损坏。 将损坏的沟槽掩模层剥离，使得半导体衬底的表面露出。

公开(公告)号：US20160133643A1

公开(公告)日：2016-05-12

申请号：US14995586

申请日：2016-01-14

申请人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

发明人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

摘要： A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

摘要翻译： 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

公开(公告)号：US08735247B2

公开(公告)日：2014-05-27

申请号：US13204349

申请日：2011-08-05

申请人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

发明人： Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Jin-Gyun Kim

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L29/76

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

摘要翻译： 公开了一种用于制造非易失性存储器件的方法。 该方法包括在半导体衬底上形成用于公共源极线的第一结构，第一结构沿着第一方向延伸，通过在半导体衬底上交替堆叠多个牺牲层和多个绝缘层来形成模具结构，形成 所述模具结构中的多个开口露出所述第一结构的一部分，以及在所述第一结构的第一侧形成第一存储单元串，以及在所述第一结构的第二相反侧形成第二存储单元串。 多个开口包括第一通孔和第二通孔，每个通孔穿过多个牺牲层和多个绝缘层，并且第一通孔和第二通孔重叠在一起 第一个方向。

公开(公告)号：US08525275B2

公开(公告)日：2013-09-03

申请号：US12916718

申请日：2010-11-01

申请人： Jin-Hwa Heo ,  Chul-Sung Kim ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Chang-Hyun Lee

发明人： Jin-Hwa Heo ,  Chul-Sung Kim ,  Bon-Young Koo ,  Ki-Hyun Hwang ,  Chang-Hyun Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28202 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518

摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.

摘要翻译： 非易失性存储器件包括电荷存储层和衬底之间的电介质层。 可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。 结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

公开(公告)号：US08445367B2

公开(公告)日：2013-05-21

申请号：US13287509

申请日：2011-11-02

申请人： Jin-Tae Noh ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

发明人： Jin-Tae Noh ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L27/1157 ,  H01L27/10855 ,  H01L27/11582

摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

摘要翻译： 在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。 绝缘夹层包括与牺牲层的材料不同的材料。 通过绝缘夹层和牺牲层形成至少一个开口。 至少一个开口露出基板。 种子层使用第一硅源气体形成在至少一个开口的内壁上。 通过种植种子层在至少一个开口中形成多晶硅沟道。 去除牺牲层以在绝缘夹层之间形成多个凹槽。 在槽中分别形成有多个栅极结构。

公开(公告)号：US20130105880A1

公开(公告)日：2013-05-02

申请号：US13564992

申请日：2012-08-02

申请人： Hong-Suk Kim ,  Yong-Seok Kim ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

发明人： Hong-Suk Kim ,  Yong-Seok Kim ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.

摘要翻译： 非易失性存储器件及其制造方法包括在衬底上的浮置栅极，在浮置栅极的上表面上包括第一下阻挡层的下势垒层和位于浮置栅极的侧表面上的第二下势垒层 浮栅的厚度小于第一下阻挡层的厚度，下阻挡层上的栅极间电介质层和栅极间电介质层上的控制栅极。