公开(公告)号：US20160087070A1

公开(公告)日：2016-03-24

申请号：US14495562

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract translation: 体硅（Si）的一部分形成为具有翅片基底的翅片，并且在散热片基底上形成有工艺中的翅片。 翅片基底是掺杂硅，而工艺中的鳍是硅锗（SiGe）。 工艺中的SiGe鳍具有源极区和漏极区。 硼原位掺杂到漏区并进入源区。 任选地，硼通过在漏极区域和源极区域上形成具有硼的外延层进行原位掺杂，以及驱动退火以在源极区域和漏极区域中扩散硼。

公开(公告)号：US20150380257A1

公开(公告)日：2015-12-31

申请号：US14849506

申请日：2015-09-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG

IPC: H01L21/308 ,  H01L21/84 ,  H01L21/3065 ,  H01L27/088

CPC classification number: H01L21/3085 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66795

Abstract: A device is fabricated on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. A first mask is formed over the surface at a first portion of the wafer, leaving a second portion of the wafer unmasked. The wafer is etched at the unmasked second portion of the wafer to form a depression in the active silicon layer. A thermal oxide layer is formed to substantially fill the depression, the first mask is removed, and fins are formed at the first and second portions of the wafer.

Abstract translation: 一种器件制造在由衬底形成的绝缘体上硅（SOI）晶片上，衬底上的底部氧化物层和底部氧化物层上的活性硅层，其中活性硅层具有与底部氧化物相对的表面 层。 在晶片的第一部分的表面上形成第一掩模，留下晶片的第二部分未被掩蔽。 在晶片的未屏蔽的第二部分处蚀刻晶片以在活性硅层中形成凹陷。 形成热氧化层以基本上填充凹陷，去除第一掩模，并且在晶片的第一和第二部分处形成翅片。

公开(公告)号：US20150333008A1

公开(公告)日：2015-11-19

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L23/535 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

Abstract translation: 标准单元CMOS器件包括具有由栅极互连形成的栅极的金属氧化物半导体晶体管。 栅极互连沿第一方向延伸。 该器件还包括向晶体管提供功率的电源轨。 电源轨在与第一方向正交的第二方向上延伸。 该装置还包括在电源轨之间延伸的M1层互连。 M1层互连中的至少一个耦合到至少一个晶体管。 M1层互连平行于栅极互连并仅在第一方向上延伸。

公开(公告)号：US20150325514A1

公开(公告)日：2015-11-12

申请号：US14274378

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A static random access memory (SRAM) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer. The SRAM cell also includes a second via coupling the wordline landing pad and the wordline of the second conductive layer.

Abstract translation: 静态随机存取存储器（SRAM）单元包括第一导电层，其包括延伸到存储器阵列的相邻行中的相邻存储器单元的字线着陆焊盘。 第一导电层中的字线着陆焊盘与相邻存储器单元的所有栅极触点电隔离。 SRAM单元还包括第二导电层，其包括耦合到第一导电层中的字线着陆焊盘的字线。 SRAM单元进一步包括将SRAM单元中的通过晶体管栅极的栅极接触耦合到第一导电层中的字线着陆焊盘的第一通孔。 SRAM单元还包括耦合字线着陆焊盘和第二导电层的字线的第二通孔。

公开(公告)号：US20150317426A1

公开(公告)日：2015-11-05

申请号：US14498939

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: Integrated circuit (IC) technology design may include binning data paths of an IC device of a current technology node to bins based on a performance of each of the data paths. Each of the plurality of bins is mapped to a representative circuit unit data path configured according to a predetermined set of electrical and/or physical parameters. The representative circuit unit data paths are calibrated according to updated electrical and/or physical parameters to increase the performance of the representative circuit unit data paths to improve the performance of the IC device in an advanced technology node.

Abstract translation: 集成电路（IC）技术设计可以包括基于每个数据路径的性能来对当前技术节点的IC设备的分组数据路径进行分组。 多个箱中的每一个被映射到根据预定的一组电和/或物理参数配置的代表性电路单元数据路径。 代表性的电路单元数据路径根据更新的电和/或物理参数进行校准，以增加代表性电路单元数据路径的性能，以提高先进技术节点中的IC器件的性能。

公开(公告)号：US20150301973A1

公开(公告)日：2015-10-22

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern RIM ,  Stanley Seungchul SONG ,  Xiangdong CHEN ,  Raymond George Stephany ,  John Jianhong ZHU ,  Ohsang KWON ,  Esin TERZIOGLU ,  Choh Fei YEAP

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Abstract translation: 设计导电互连的方法包括至少部分地基于互连迹线间距和指定单元高度的整数倍来确定残余间隔值。 该方法还包括将剩余间隔分配到互连迹线间距内的至少一个互连迹线宽度或互连迹线空间。

公开(公告)号：US20150194339A1

公开(公告)日：2015-07-09

申请号：US14283162

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU ,  Xiangdong CHEN ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/76814 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.

Abstract translation: 制造中间线（MOL）层和包括MOL层的器件的方法。 根据本公开的一个方面的方法包括将半导体衬底的半导体器件的端子上的活性触点沉积硬掩模。 这种方法还包括图案化硬掩模以选择性地暴露一些有源触点并选择性地绝缘一些有源触点。 该方法还包括在图案化的硬掩模和暴露的有源触点上沉积导电材料，以将暴露的有源触点彼此连接在半导体器件的有效区域上。

公开(公告)号：US20150144962A1

公开(公告)日：2015-05-28

申请号：US14322207

申请日：2014-07-02

Applicant: QUALCOMM Incorporated

Inventor： Kern RIM ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161

Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.

Abstract translation: 互补翅片场效应晶体管（FinFET）包括具有p沟道鳍片的p型器件。 p沟道鳍可以包括相对于半导体衬底而晶格失配的第一材料。 第一种材料可能具有压缩应变。 FinFET器件还包括具有再通道鳍片的n型器件。 n沟道翅片可以包括具有相对于半导体衬底的晶格失配的拉伸应变的第二材料。 p型器件和n型器件配合形成互补FinFET器件。

公开(公告)号：US20140313821A1

公开(公告)日：2014-10-23

申请号：US14320897

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Mohamed Hassan ABU-RAHMA ,  Beom-Mo HAN

IPC: H01L29/78 ,  G11C11/40 ,  H01L29/66

CPC classification number: H01L29/785 ,  G11C11/40 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7841 ,  H01L29/7855 ,  H01L29/78648

Abstract: A fin-type device system and method is disclosed. In a particular embodiment, a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.

Abstract translation: 公开了一种翅片式装置系统和方法。 在特定实施例中，公开了晶体管，并且包括在衬底内形成晶体管的栅极，所述衬底具有衬底内的表面和掩埋氧化物（BOX）层，并且在第一BOX层面处与栅极相邻。 该方法还包括升高的源 - 漏通道（“鳍”），其中鳍的至少一部分从衬底的表面延伸，并且其中鳍具有与第二BOX层的第二BOX层面相邻的第一鳍面 BOX层。