公开(公告)号：US20130137213A1

公开(公告)日：2013-05-30

申请号：US13677663

申请日：2012-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuji EGI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/0206 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/465 ,  H01L21/4757 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/14616 ,  H01L29/045 ,  H01L29/0684 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78693

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

公开(公告)号：US20220416061A1

公开(公告)日：2022-12-29

申请号：US17902224

申请日：2022-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Masashi TSUBUKU

IPC: H01L29/66 ,  H01L27/12 ,  H01L27/146 ,  H01L21/02 ,  H01L29/786

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US20210384353A1

公开(公告)日：2021-12-09

申请号：US16637384

申请日：2018-08-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuta ENDO ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/12

Abstract: A semiconductor device that can be highly integrated is provided.
The semiconductor device includes first and second transistors and first and second capacitors. Each of the first and second transistors includes a gate insulator and a gate electrode over an oxide. Each of the first and second capacitors includes a conductor, a dielectric over the conductor, and the oxide. The first and second transistors are provided between the first capacitor and the second capacitor. One of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is also used as one electrode of the first capacitor. The other of the source and the drain of the second transistor is also used as one electrode of the second capacitor. The channel lengths of the first and second transistors are larger than the lengths in a direction parallel to short sides of fourth and fifth conductors.

公开(公告)号：US20210082967A1

公开(公告)日：2021-03-18

申请号：US17106860

申请日：2020-11-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Koji Ono ,  Hideomi SUZAWA

IPC: H01L27/12 ,  C23F4/00 ,  H01L21/3213 ,  H01L21/768 ,  H01B1/02 ,  H01B5/14 ,  H01B13/00 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

公开(公告)号：US20210057586A1

公开(公告)日：2021-02-25

申请号：US16923160

申请日：2020-07-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/04 ,  H01L27/105 ,  H01L27/12 ,  H01L27/146 ,  H01L29/24 ,  H01L29/66

Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.

公开(公告)号：US20190103478A1

公开(公告)日：2019-04-04

申请号：US16194444

申请日：2018-11-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Masashi TSUBUKU

IPC: H01L29/66 ,  H01L27/146 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US20180248010A1

公开(公告)日：2018-08-30

申请号：US15903097

申请日：2018-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/423 ,  H01L27/146

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US20180151750A1

公开(公告)日：2018-05-31

申请号：US15879023

申请日：2018-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Yuhei SATO ,  Sachiaki TEZUKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L27/12 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/78648 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

公开(公告)号：US20180108680A1

公开(公告)日：2018-04-19

申请号：US15837552

申请日：2017-12-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Taiga MURAOKA

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1343 ,  G09G3/36 ,  G09F21/04 ,  G02F1/167 ,  G02F1/1362 ,  G11C19/28 ,  H01L27/32

CPC classification number: H01L27/127 ,  G02F1/134309 ,  G02F1/136227 ,  G02F1/167 ,  G09F21/04 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0809 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

公开(公告)号：US20170323974A1

公开(公告)日：2017-11-09

申请号：US15597237

申请日：2017-05-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78648

Abstract: A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.