-
公开(公告)号：US12046987B2
公开(公告)日：2024-07-23
申请号：US17582431
申请日：2022-01-24
CPC分类号： H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
-
公开(公告)号：US11894052B2
公开(公告)日：2024-02-06
申请号：US17718908
申请日：2022-04-12
发明人： Marco Pasotti , Marcella Carissimi , Alessio Antolini , Eleonora Franchi Scarselli , Antonio Gnudi , Andrea Lico , Paolo Romele
CPC分类号： G11C13/0061 , G11C13/0004 , G11C13/0026 , G11C13/0038
摘要： An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
-
公开(公告)号：US10978146B2
公开(公告)日：2021-04-13
申请号：US16662911
申请日：2019-10-24
摘要： A phase-change memory device, comprising: a memory array of PCM cells, a variable current generator, and a sense amplifier. The current generator comprises a reference array of PCM cells programmed in SET resistance state. The phase-change memory device further comprises a decoder for addressing each cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; and a controller configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current to be lower than said mean value.
-
公开(公告)号：US10755777B2
公开(公告)日：2020-08-25
申请号：US16169763
申请日：2018-10-24
摘要： The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.
-
公开(公告)号：US09627066B1
公开(公告)日：2017-04-18
申请号：US15210709
申请日：2016-07-14
CPC分类号： G11C16/0441 , G11C16/04 , G11C16/0408 , G11C16/10 , G11C16/14 , G11C16/26
摘要： A non-volatile memory cell for storing a single bit is disclosed. The non-volatile memory cell includes an access transistor including a gate, a first body, a first source/drain node, and a second source/drain node. The non-volatile memory cell also includes a first floating gate storage transistor that has a third source/drain node, a second body, a fourth source/drain node, and a first floating gate including a first storage node. The third source/drain node is coupled to the second source/drain node. The non-volatile memory cell further includes a first capacitor, a second capacitor, and a second floating gate storage transistor. The first capacitor has a first plate coupled to the first storage node and an opposite second plate. The second floating gate storage transistor includes a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate including a second storage node. The fifth source/drain node is coupled to the fourth source/drain node. The second capacitor includes a third plate coupled to the second storage node and having an opposite fourth plate. The second plate is coupled to the fourth plate, and the first body of the access transistor is coupled to the second body and the third body.
-
56.发明授权Identification of a condition of a sector of memory cells in a non-volatile memory 有权识别非易失性存储器中的存储器单元的扇区的状况公开(公告)号：US09443566B2
公开(公告)日：2016-09-13
申请号：US14061977
申请日：2013-10-24
摘要： An embodiment solution for operating a non-volatile memory of a complementary type is proposed. The non-volatile memory includes a plurality of sectors of memory cells, each memory cell being adapted to take a programmed state or an erased state. Moreover, the memory cells are arranged in locations each formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. In an embodiment, a corresponding method includes the following steps: selecting at least one of the sectors, determining an indication of the number of memory cells in the programmed state and an indication of the number of memory cells in the erased state of the selected sector, and identifying the condition of the selected sector according to a comparison between the indication of the number of memory cells in the programmed state and the indication of the number of memory cells in the erased state.
摘要翻译： 提出了用于操作互补型非易失性存储器的实施例解决方案。 非易失性存储器包括存储器单元的多个扇区，每个存储器单元适于采取编程状态或擦除状态。 此外，存储单元被布置在由直接存储单元和互补存储单元形成的位置中。 当相应的存储器单元处于相同的状态并且处于写入状态时，非易失性存储器的每个扇区处于非写入状态，其中当其中的每个位置存储第一逻辑值或第二逻辑值时， 位置分别处于不同状态的第一组合或处于不同状态的第二组合中。 在一个实施例中，相应的方法包括以下步骤：选择扇区中的至少一个，确定编程状态下的存储器单元的数量的指示以及所选扇区的擦除状态中的存储器单元的数量的指示 并且根据编程状态下的存储单元的数量的指示与擦除状态下的存储单元的数量的指示之间的比较来识别所选扇区的状况。
-
公开(公告)号：US09286160B2
公开(公告)日：2016-03-15
申请号：US14175843
申请日：2014-02-07
CPC分类号： G06F11/1076 , G06F11/1048 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2029/0411 , G11C2211/5646
摘要： According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.
摘要翻译： 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。
-
-
-
-
-
-
搜索结果
57 条记录 (耗时 0.022 秒)
