公开(公告)号：US09020053B2

公开(公告)日：2015-04-28

申请号：US13612099

申请日：2012-09-12

申请人： Scott C. Best

发明人： Scott C. Best

IPC分类号： H04K1/10 ,  H04L27/28 ,  G06F1/06

CPC分类号： G06F1/06

摘要： Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example.

摘要翻译： 以下提供了时钟系统和方法，以精确地对每个集成电路设备的输入/输出（IO）电路的每针数据传输进行时钟计时。 这些基于多路复用器的时钟选择系统使用专用多路复用器来接收来自多个混频器电路的时钟信号，并且进而提供选择的参考时钟信号，供接口电路用于将数据传送到其它集成电路器件。 所选参考时钟信号的定时与数据信号同步，以提供数据信号的最佳采样。 基于多路复用器的时钟选择系统例如用于高速信号系统的存储器接口中。

公开(公告)号：US08737106B2

公开(公告)日：2014-05-27

申请号：US13562242

申请日：2012-07-30

申请人： Scott C. Best ,  Ming Li

发明人： Scott C. Best ,  Ming Li

IPC分类号： G11C5/02

CPC分类号： G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multi-die memory device includes a first die of a first type and configured to electrically interface with an external processor via a first synchronous interface operating at a first clock rate, and at least one second die of a second type and configured for data storage. Each second die transacts data with the first die via a second synchronous interface operating at a second clock rate, where the first clock rate is an integer multiple of the second clock rate, and where a timing reference associated with the second synchronous interface is transmitted by the first die to the second die.

摘要翻译： 多管芯存储器件包括第一类型的第一管芯，并且被配置为经由第一时钟速率操作的第一同步接口和至少一个第二类型的第二管芯与外部处理器电接口并被配置用于数据存储 。 每个第二管芯经由经由第二时钟速率工作的第二同步接口与第一管芯交换数据，其中第一时钟速率是第二时钟速率的整数倍，并且其中与第二同步接口相关联的定时参考通过 第一个死亡到第二个死亡。

公开(公告)号：US20120327726A1

公开(公告)日：2012-12-27

申请号：US13578864

申请日：2010-12-01

申请人： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

发明人： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C7/00

CPC分类号： G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

摘要翻译： 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US08332680B2

公开(公告)日：2012-12-11

申请号：US12220453

申请日：2008-07-24

申请人： Scott C. Best

发明人： Scott C. Best

IPC分类号： G06F1/12 ,  G06F13/42 ,  G06F1/00 ,  G06F13/00 ,  G06F13/28 ,  H04L5/00

CPC分类号： G06F13/4265 ,  G06F13/1668

摘要： A memory system permits synchronized transmission of data with multiple memory modules in a dynamically expandable bus system such as with a point-to-point memory bus using strobed data transmission. Memory modules of the system are selectively configured to switch transmission modes to either transmit data to a memory controller or a timing reference signal to another memory module from a common terminal coupled to a common path of the bus which may depend on the number of memory modules configured in the system. The system permits all memory modules to operate with a strobed based memory controller even when some memory modules of the system do not share a strobe signal path with the memory controller of the system.

摘要翻译： 存储器系统允许在动态扩展的总线系统中使用诸如使用选通数据传输的点对点存储器总线的数据与多个存储器模块的同步传输。 系统的存储器模块被选择性地配置为切换传输模式，以将数据从存储器控制器传送到另一存储器模块，或者将定时参考信号从耦合到总线的公共路径的公共端子发送到另一个存储器模块，这可以取决于存储器模块的数量 在系统中配置。 该系统允许所有存储器模块使用基于选通的存储器控​​制器进行操作，即使系统的某些存储器模块不与系统的存储器控​​制器共享选通信号路径。

公开(公告)号：US08311761B2

公开(公告)日：2012-11-13

申请号：US13276708

申请日：2011-10-19

申请人： Scott C. Best

发明人： Scott C. Best

IPC分类号： G01R35/00

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/222

摘要： A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

摘要翻译： 公开了一种在存储器控制器中的操作方法。 该方法包括：接收相对于在第一数据线上传播的第一数据具有第一相位关系的选通信号，以及相对于在第二数据线上传播的第二数据的第二相位关系。 基于第一相位关系产生第一采样信号，并且基于第二相位关系生成第二采样信号。 使用由第一采样信号计时的第一接收机接收第一数据信号。 使用由第二采样信号计时的第二接收机接收第二数据信号。

公开(公告)号：US08270501B2

公开(公告)日：2012-09-18

申请号：US10921576

申请日：2004-08-18

申请人： Scott C. Best

发明人： Scott C. Best

IPC分类号： H04K1/10 ,  H04L27/28

CPC分类号： G06F1/06

摘要： Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example.

摘要翻译： 以下提供了时钟系统和方法，以精确地对每个集成电路设备的输入/输出（IO）电路的每针数据传输进行时钟计时。 这些基于多路复用器的时钟选择系统使用专用多路复用器来接收来自多个混频器电路的时钟信号，并且进而提供选择的参考时钟信号，供接口电路用于将数据传送到其它集成电路器件。 所选参考时钟信号的定时与数据信号同步，以提供数据信号的最佳采样。 基于多路复用器的时钟选择系统例如用于高速信号系统的存储器接口中。

公开(公告)号：US20120147979A1

公开(公告)日：2012-06-14

申请号：US13391223

申请日：2010-03-30

申请人： Scott C. Best ,  John W. Poulton

发明人： Scott C. Best ,  John W. Poulton

IPC分类号： H04L27/00

CPC分类号： G11C5/144 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0793 ,  G06F13/4072 ,  G11C5/145 ,  H04L1/203 ,  H04L25/0264 ,  H04L25/08

摘要： In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

摘要翻译： 在数据传输系统中，在第一电路中生成用于产生要发送的信号的信令电压的一个或多个信号电源电压，并从第一电路转发到第二电路。 第二电路可以使用转发的信号电源电压来产生要从第二电路传输回第一电路的另一个信号，从而避免在第二电路中单独产生信号电源电压的需要。 第一电路还可以基于从第二电路传输回第一电路的信号来调整信号电源电压。 数据传输系统可以使用单端信令系统，其中信令电压参考作为由第一电路和第二电路共享的诸如地的电源电压的参考电压。

公开(公告)号：US20110016278A1

公开(公告)日：2011-01-20

申请号：US12920811

申请日：2009-03-05

申请人： Frederick Ware ,  Craig E. Hampel ,  Ian Shaeffer ,  Scott C. Best

发明人： Frederick Ware ,  Craig E. Hampel ,  Ian Shaeffer ,  Scott C. Best

IPC分类号： G06F12/00

CPC分类号： G11C7/1072 ,  G06F13/1684 ,  G06F13/4234 ,  G11C5/00

摘要： A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.

摘要翻译： 存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。 多个存储器件安装在基片上。 每个存储器件耦合到控制路径和不同的数据路径。 存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

公开(公告)号：US20100135370A1

公开(公告)日：2010-06-03

申请号：US12527005

申请日：2008-02-28

申请人： Scott C. Best

发明人： Scott C. Best

IPC分类号： H04B1/38 ,  H04L27/00

CPC分类号： H04L25/0264 ,  G06F13/4072 ,  H04L5/1469 ,  H04L5/16

摘要： A bi-directional interface circuit includes a transmitter portion, a receiver portion, a current source bias circuit, and a switch. When the interface circuit is transmitting data, the switch steers the bias current generated by the current source bias circuit to the transmitter portion of the interface. When the interface is receiving data, the switch steers the bias current to the receiver portion of the interface. Thus, the current-source bias circuit is kept on regardless of whether the interface is transmitting or receiving data. Because the current-source bias circuit is not turned on and off, the switching noise generated when the interface transitions between transmitting and receiving operations is eliminated or reduced. Consequently, any dead time inserted for such a transition can be minimized, and the effective bandwidth of the interface is increased.

摘要翻译： 双向接口电路包括发射机部分，接收机部分，电流源偏置电路和开关。 当接口电路正在发送数据时，开关将由电流源偏置电路产生的偏置电流转向接口的发射器部分。 当接口接收数据时，交换机将偏置电流引导到接口的接收器部分。 因此，无论接口是发送还是接收数据，电流源偏置电路都保持不变。 由于电流源偏置电路没有导通和截止，所以在发送和接收操作之间的接口转换时产生的开关噪声被消除或减少。 因此，可以将为这种转换插入的任何死区时间最小化，并且增加接口的有效带宽。

公开(公告)号：US20090282189A1

公开(公告)日：2009-11-12

申请号：US12505438

申请日：2009-07-17

申请人： Scott C. Best ,  Ely K. Tsern

发明人： Scott C. Best ,  Ely K. Tsern

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

摘要： A memory controller is disclosed that provides refresh control circuitry to generate first refresh commands directed to a first row of storage cells within a memory device at a first rate. The refresh control circuitry generates second refresh commands directed to a second row of storage cells within the memory device at a second rate. Output circuitry outputs the first and second refresh commands to the memory device.

摘要翻译： 公开了一种存储器控制器，其提供刷新控制电路以第一速率产生定向到存储器设备内的第一行存储单元的第一刷新命令。 刷新控制电路以第二速率产生定向到存储器装置内的第二行存储单元的第二刷新命令。 输出电路将第一和第二刷新命令输出到存储器件。