公开(公告)号：US20160357631A1

公开(公告)日：2016-12-08

申请号：US15238839

申请日：2016-08-17

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen

IPC: G06F11/10 ,  H03M13/11 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0676 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1072 ,  G06F2206/1014 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to trade the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Abstract translation: 对于从SLC NVM（或MLC的下页）读取的每个读取单元，SSD控制器维持零计数和一个计数，和/或在一些实施例中为零/一个视差计数。 在读取单元部分由于阈值电压分布远离其标称分布的偏移而不能校正的情况下，维持的计数使得能够确定方向和/或幅度以调整读取阈值以交换阈值电压 移位并恢复读数据零/一个余额。 在各种实施例中，基于所描述的因素的数量（确定的阈值电压分布，已知存储值，过去的NVM操作事件）以各种描述的方式（计数，百分比）来确定调整的读取阈值。 对于MLC存储器描述了前述技术的扩展。

公开(公告)号：US09443616B2

公开(公告)日：2016-09-13

申请号：US14263189

申请日：2014-04-28

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Earl T. Cohen ,  Erich F. Haratsch ,  Jeremy Werner

IPC: G11C29/44 ,  G11C29/26 ,  G11C29/38 ,  G11C29/00 ,  G11C29/04 ,  G06F11/07 ,  G11C29/42 ,  G11C29/52 ,  G11C16/34

CPC classification number: G11C29/44 ,  G06F11/07 ,  G06F11/0727 ,  G06F11/073 ,  G11C16/349 ,  G11C29/26 ,  G11C29/38 ,  G11C29/42 ,  G11C29/52 ,  G11C29/765 ,  G11C2029/0403 ,  G11C2029/0409

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory unit granularities each having a size less than a total size of the memory. The controller is configured to process a plurality of I/O requests to the memory units of the memory that are not marked as bad on a memory unit list. The controller is configured to track a plurality of bad blocks of the memory. The controller is configured to determine which of the memory units to mark as bad based on a test of whether a unit of memory larger than a block of the memory has failed. The test is based on a threshold of the bad blocks in the unit of memory.

Abstract translation: 一种包括存储器和控制器的装置。 存储器被配置为处理多个读/写操作。 存储器包括多个存储器单元粒度，每个存储器单元的尺寸小于存储器的总大小。 控制器被配置为处理对存储器单元列表中未被标记为坏的存储器单元的多个I / O请求。 控制器被配置为跟踪存储器的多个坏块。 控制器被配置为基于是否大于存储器块的存储器单元失败的测试来确定哪个存储器单元被标记为坏。 该测试基于内存单元中的坏块的阈值。

公开(公告)号：US09367389B2

公开(公告)日：2016-06-14

申请号：US13804495

申请日：2013-03-14

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Earl T. Cohen ,  Yunxiang Wu

IPC: G06F11/10 ,  H03M13/45 ,  G11C29/52 ,  G11C16/34

CPC classification number: G06F11/1048 ,  G06F11/1072 ,  G11C16/34 ,  G11C16/3404 ,  G11C29/52 ,  H03M13/458

Abstract: A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window, and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window.

Abstract translation: 在读通道中应用感测/读取参考电压序列的方法包括（A）基于读通道的估计设置读窗口，（B）设置感测电压序列的第一，第二和第三值 对应于（i）读取窗口的左侧限制，（ii）读取窗口的右侧限制和（iii）读取窗口中心点的不同值的值，（C）确定是否 第一，第二和第三读取成功，（D）如果第一，第二和第三读取不成功，则将感测电压序列的第四和第五值设置为对应于（i） 左侧限制和读取窗口中心的点，以及（ii）右侧限制和读取窗口中心点之间的点。

公开(公告)号：US09317361B2

公开(公告)日：2016-04-19

申请号：US14100280

申请日：2013-12-09

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Earl T. Cohen

IPC: H03M13/00 ,  G06F11/10

CPC classification number: G06F11/1012

Abstract: An apparatus having a device and a circuit is disclosed. The device has a plurality of bit-lines and is configured to store a codeword. The circuit is configured to (i) receive the codeword from the device, (ii) generate a syndrome by performing a portion less than all of an iterative decoding procedure on the codeword and (iii) generate a map of defects according to the syndrome. Each of a plurality of bits in the map corresponds to a respective one of the bit-lines.

Abstract translation: 公开了一种具有装置和电路的装置。 该设备具有多个位线，并且被配置为存储码字。 电路被配置为（i）从设备接收码字，（ii）通过执行小于码字上的全部迭代解码过程的部分来产生综合征，以及（iii）根据综合征产生缺陷图。 地图中的多个比特中的每一个对应于相应的一个比特线。

公开(公告)号：US20160070496A1

公开(公告)日：2016-03-10

申请号：US14942475

申请日：2015-11-16

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen ,  Timothy L. Canepa

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0616 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/7206 ,  G06F2212/7207 ,  G06F2212/7208 ,  G06F2212/7211 ,  Y02D10/13

Abstract: Method and apparatus for managing data in a Non-Volatile Memory (NVD). In some embodiments, management information is stored in a buffer memory using a Solid-State Disk (SSD) controller circuit, the management information comprising a map data structure that associates storage addresses of a host device to physical addresses of the NVD. A location in the management information is determined responsive to a selected host storage address and a programmable parameter by arithmetically dividing in accordance with a divisor specified at least in part by the programmable parameter. The location in the management information is used to direct a transfer of user data by the SSD control circuit between the host device and the NVM.

Abstract translation: 用于管理非易失性存储器（NVD）中的数据的方法和装置。 在一些实施例中，使用固态盘（SSD）控制器电路将管理信息存储在缓冲存储器中，所述管理信息包括将主机设备的存储地址与NVD的物理地址相关联的地图数据结构。 根据至少部分地由可编程参数指定的除数通过算术分割来响应所选择的主机存储地址和可编程参数来确定管理信息中的位置。 管理信息中的位置用于在主机设备和NVM之间引导SSD控制电路传送用户数据。

公开(公告)号：US09213633B2

公开(公告)日：2015-12-15

申请号：US13889521

申请日：2013-05-08

Applicant: Seagate Technology LLC

Inventor： Timothy L. Canepa ,  Earl T. Cohen ,  Alex G. Tang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A method of associating a logical block address with a physical location in a non-volatile memory includes (A) in response to a write request comprising a respective logical block address in a logical block address space and respective data to be written to the non-volatile memory, determining a physical location in the non-volatile memory to store the respective data of the write request, (B) adding an entry to a journal, such that the added entry trails any entries already in the journal and the added entry has a respective logical block address field set to the respective logical block address of the write request and a respective physical location field set to the determined physical location, and (C) updating one of a plurality of second-level map pages in a two-level map according to the respective logical block address of the write request with the determined physical location.

Abstract translation: 将逻辑块地址与非易失性存储器中的物理位置相关联的方法包括（A）响应于包括逻辑块地址空间中的相应逻辑块地址的写请求以及要写入非易失性存储器的相应数据， 确定非易失性存储器中的物理位置以存储写入请求的相应数据，（B）将条目添加到日志，使得添加的条目跟踪已经在日志中的任何条目，并且添加的条目具有 设置到写请求的相应逻辑块地址的相应逻辑块地址字段和设置到所确定的物理位置的相应物理位置字段，以及（C）更新两级中的多个二级地图页之一 根据具有确定的物理位置的写请求的相应逻辑块地址映射。

公开(公告)号：US09213602B1

公开(公告)日：2015-12-15

申请号：US14311645

申请日：2014-06-23

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Erich F. Haratsch ,  Earl T. Cohen ,  Yunxiang Wu

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/52 ,  H03M13/45 ,  G11C29/54

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1068 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C27/005 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/256 ,  H03M13/2906 ,  H03M13/45 ,  H03M13/458

Abstract: An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states.

Abstract translation: 具有映射和接口电路的装置。 映射电路（i）通过使用过去位的调制或递归映射写入单元比特来生成编码项，并且（ii）计算特定状态以编程到非易失性存储单元中。 接口电路在特定状态下对单元进行编程。 两个正常的细胞状态被视为至少四个精细状态。 特定状态是精细状态之一。 对精细状态的映射减轻了将单元的模拟电压从特定状态转移到错误状态的编程写入错位。 错误状态对应于易于观察的非法或非典型写入序列，并且导致仅基于正常状态计算出的修改的软判决。 特定状态和错误状态之间的电压摆动小于正常状态之间的电压摆动。

公开(公告)号：US20150278015A1

公开(公告)日：2015-10-01

申请号：US14697904

申请日：2015-04-28

Applicant: Seagate Technology LLC

Inventor： Erich F. Haratsch ,  Jeremy Werner ,  Zhengang Chen ,  Earl T. Cohen ,  Yunxiang Wu ,  Ning Chen

IPC: G06F11/10 ,  H03M13/45 ,  H03M13/11 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/3905 ,  H03M13/41 ,  H03M13/45 ,  H03M13/6561

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.

Abstract translation: 一种包括存储器和控制器的装置。 存储器可以被配置为存储数据。 控制器可以处理多个输入/输出请求以从/从存储器读/写。 控制器可以通过对从存储器接收的码字执行硬判决解码来生成读数据。 如果硬判决解码失败，则控制器可以进入包括多个恢复过程的错误恢复过程。 至少一个恢复过程可以应用小区间干扰消除技术。 错误恢复过程可以（a）通过执行码字上的恢复过程之一来确定软判决解码的参数，（b）使用执行的恢复过程的参数来执行软判决解码以产生读取数据 和（c）如果软判决解码失败，请重复（a）和（b）使用下一个恢复过程。

公开(公告)号：US09122587B2

公开(公告)日：2015-09-01

申请号：US13796264

申请日：2013-03-12

Applicant: Seagate Technology LLC

Inventor： Leonid Baryudin ,  Earl T. Cohen ,  Alex G. Tang

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7209

Abstract: An apparatus having a nonvolatile memory and a controller. The memory stores information in multiple pages. The information includes data units and headers. Each data unit is associated with a respective identifier in an address space of the apparatus and a respective location in the memory, has a respective header having the respective identifier, and is associated with a respective time stamp. Multiple headers include ones of the time stamps. The controller is configured to (i) read information stored in the pages, (ii) determine an order in which the data units were written based on the time stamps, (iii) locate based on the order (a) each last-written occurrence of the respective identifiers and (b) the respective locations of the data units associated with the last-written occurrences, and (iv) rebuild a map of the controller according to the respective locations of each last-written occurrence of each respective identifier.

Abstract translation: 具有非易失性存储器和控制器的装置。 内存将信息存储在多个页面中。 信息包括数据单元和标题。 每个数据单元与设备的地址空间中的相应标识符相关联，并且存储器中的相应位置具有相应标题，并且与相应的时间戳相关联。 多个标题包括时间戳中的一个。 控制器被配置为（i）读取存储在页面中的信息，（ii）基于时间戳确定写入数据单元的顺序，（iii）基于顺序（a）每个最后写入的事件 和（b）与最后写入的事件相关联的数据单元的相应位置，以及（iv）根据每个相应标识符的每个最后写入的发生的相应位置来重建控制器的映射。

公开(公告)号：US09081666B2

公开(公告)日：2015-07-14

申请号：US13768215

申请日：2013-02-15

Applicant: Seagate Technology LLC

Inventor： Christopher Brewer ,  Earl T. Cohen

IPC: G06F13/00 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04 ,  G06F9/38

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/38 ,  G06F12/0246 ,  G06F13/1694 ,  G06F13/385 ,  G11C5/04

Abstract: A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface.

Abstract translation: 系统包括控制处理器，非易失性存储器件接口和微定序器。 控制处理器可以被配置为经由命令接口接收命令并发送响应。 非易失性存储器设备接口可以被配置为将系统耦合到一个或多个非易失性存储器设备。 微定序器通常耦合到（i）控制处理器和（ii）非易失性存储器件接口。 微定序器包括可由微定序器读取并由控制处理器写入的控制存储器。 响应于接收到特定的一个命令，控制处理器能够使得微定序器根据特定命令开始在控制存储器中的一个位置执行，并且微定序器能够执行至少一部分 根据耦合到非易失性存储器设备接口的一个或多个非易失性存储器件的协议来执行特定命令。