公开(公告)号：US10409518B1

公开(公告)日：2019-09-10

申请号：US15493102

申请日：2017-04-20

Applicant: Seagate Technology LLC

Inventor： Hongmei Xie ,  AbdelHakim Alhussien ,  Sundararajan Sankaranarayanan ,  Alex Tang ,  Leonid Baryudin ,  Erich Franz Haratsch

IPC: G06F3/06

Abstract: A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.

公开(公告)号：US10276233B1

公开(公告)日：2019-04-30

申请号：US15799484

申请日：2017-10-31

Applicant: Seagate Technology LLC

Inventor： Ludovic Danjean ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time; shift the plurality of read reference voltages using the at least one reference voltage offset; and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after a predefined time interval since a programming of the multi-level memory cells.

公开(公告)号：US10177787B1

公开(公告)日：2019-01-08

申请号：US14856674

申请日：2015-09-17

Applicant: Seagate Technology LLC

Inventor： Ludovic Danjean ,  Sundararajan Sankaranarayanan ,  Ivana Djurdjevic ,  AbdelHakim Alhussien ,  Erich F. Haratsch

IPC: H03M13/11 ,  H03M13/00 ,  G06F11/10

Abstract: An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.

公开(公告)号：US20180012663A1

公开(公告)日：2018-01-11

申请号：US15639052

申请日：2017-06-30

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11

CPC classification number: G11C16/26 ,  G06F11/1012 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1105 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/3723 ,  H03M13/612 ,  H03M13/6325

Abstract: Independent read threshold voltage tracking techniques are provided for multiple dependent read threshold voltages using syndrome weights. An exemplary method comprises reading codewords of a plurality of pages using different first read threshold voltages and a default second read threshold voltage; applying read values for the plurality of pages for the different first read threshold voltages and the default second read threshold voltage to a decoder; aggregating a syndrome weight for each failed decoding attempt for the different first read threshold voltages; identifying a reading having a substantially minimum syndrome weight as a substantially optimum first read threshold voltage; reading codewords of the plurality of pages using the substantially optimum first read threshold voltage and different second read threshold voltages; applying read values for the substantially optimum first read threshold voltage and the different second read threshold voltages to the decoder; aggregating the syndrome weight for the different second read threshold voltages; and identifying a reading having a substantially minimum syndrome weight as a substantially optimum second read threshold voltage.

公开(公告)号：US20170236592A1

公开(公告)日：2017-08-17

申请号：US15496498

申请日：2017-04-25

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/26 ,  G11C29/50 ,  G06F11/10 ,  G11C16/34

CPC classification number: G11C16/26 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1068 ,  G06F12/02 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/5004 ,  H03M13/05 ,  H03M13/1111 ,  H03M13/3746 ,  H03M13/6325

Abstract: A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages. Once the predefined limit is reached, the following exemplary steps are performed: (i) mapping the readings to a corresponding likelihood value using different likelihood value assignments, and (ii) recording a syndrome weight for failed decoding attempts of the readings using the different likelihood value assignments; and using a given read threshold voltage and/or a likelihood value assignment associated with a substantially minimum syndrome weight as an initial read threshold voltage and/or a higher priority read threshold voltage for subsequent read retry operations.

公开(公告)号：US20170162268A1

公开(公告)日：2017-06-08

申请号：US15440225

申请日：2017-02-23

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan

IPC: G11C16/28 ,  G06F11/14 ,  G06F3/06 ,  G11C11/56

CPC classification number: G11C16/28 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1402 ,  G11C7/14 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028

Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.

公开(公告)号：US09417797B2

公开(公告)日：2016-08-16

申请号：US14299195

申请日：2014-06-09

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan ,  Yunxiang Wu

IPC: G11C16/28 ,  G06F3/06 ,  G11C16/26

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/28

Abstract: An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.

Abstract translation: 由闪存系统执行的自适应信道跟踪算法获得视差度量和导数度量，并且使用视差和微分度量的组合来估计最佳读取参考电压。 最佳读取参考电压的估计不依赖于下面的单元电压分布的假设，并导致读取参考电压的良好估计，即使单元电压分布的标准偏差不同。 此外，与已知的跟踪算法相比，该算法相对简单，计算量较少。

公开(公告)号：US20160093396A1

公开(公告)日：2016-03-31

申请号：US14961865

申请日：2015-12-07

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S Alhussien ,  Erich F Haratsch ,  Sundararajan Sankaranarayanan ,  YingQuan Wu

IPC: G11C16/28 ,  G11C29/42 ,  G11C16/08 ,  G11C16/26 ,  G11C29/02

CPC classification number: G11C16/28 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/26 ,  G11C29/026 ,  G11C29/028 ,  G11C29/42 ,  G11C2029/4402 ,  H03M13/1117 ,  H03M13/1125

Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.

公开(公告)号：US20150355838A1

公开(公告)日：2015-12-10

申请号：US14299195

申请日：2014-06-09

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  Erich F. Haratsch ,  Sundararajan Sankaranarayanan ,  Yunxiang Wu

IPC: G06F3/06 ,  G11C16/28

CPC classification number: G06F3/061 ,  G06F3/0653 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/28

Abstract: An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.

Abstract translation: 由闪存系统执行的自适应信道跟踪算法获得视差度量和导数度量，并且使用视差和微分度量的组合来估计最佳读取参考电压。 最佳读取参考电压的估计不依赖于下面的单元电压分布的假设，并导致读取参考电压的良好估计，即使单元电压分布的标准偏差不同。 此外，与已知的跟踪算法相比，该算法相对简单，计算量较少。

公开(公告)号：US20140160590A1

公开(公告)日：2014-06-12

申请号：US13712913

申请日：2012-12-12

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Sundararajan Sankaranarayanan ,  Raman Venkataranmani ,  William Michael Radich

IPC: G11B5/09

CPC classification number: G11B5/09 ,  G11B5/012 ,  G11B5/02 ,  G11B5/3977 ,  G11B20/10046 ,  G11B20/10212 ,  G11B2020/10953

Abstract: Detecting track information involves receiving first and second overlapping track signals from first and second read elements that read first and second tracks from a data storage medium. Information of the first and second tracks is estimated using the respective first and second track signals. An improved information estimate of the first track is obtained using the first track signal and the estimated information of the second track, and an improved information estimate of the second track is obtained using the second track signal and the estimated information of the first track. First and second track data are decoded using the respective improved information estimates of the first and second tracks.

Abstract translation: 检测轨道信息涉及从第一和第二读取元件接收从数据存储介质读取第一和第二轨道的第一和第二重叠轨道信号。 使用相应的第一和第二轨道信号来估计第一和第二轨道的信息。 使用第一轨道信号和第二轨道的估计信息获得第一轨道的改进的信息估计，并且使用第二轨道信号和第一轨道的估计信息来获得第二轨道的改进的信息估计。 第一和第二轨道数据使用第一和第二轨道的相应改进的信息估计被解码。