公开(公告)号：US06731567B2

公开(公告)日：2004-05-04

申请号：US10350482

申请日：2003-01-24

申请人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

发明人： Pramod Acharya ,  Stefan Dietrich ,  Sabine Kieser ,  Peter Schroegmeier

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C11/4093 ,  G11C2207/107

摘要： The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length. To make transferring the data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable, the invention involves an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronous with the data block signal and outputting it to a bus upon receipt of an output signal which is synchronous with the system clock signal.

摘要翻译： 本发明涉及DDR存储器和存储方法，用于将数据存储在具有多个存储单元的DDR存储器中，每个存储器单元具有规定的字长，其中使用串行数据输入来读取串行数据上升或 数据时钟信号的下降沿和串行 - 并行转换器用于将从读取的数据中的规定数量的数据项组合在一起，以从具有规定字长的数据字中给出规定数量的字。为了传送 数据从一个同步区域到另一个同步区域，并且其再同步更可靠，本发明涉及一种接收存储器，该接口存储器在接收到与数据块信号同步的复制信号时从串行 - 并行转换器复制至少一个数据字 并在接收到与系统时钟信号同步的输出信号时将其输出到总线。

公开(公告)号：US6028815A

公开(公告)日：2000-02-22

申请号：US258940

申请日：1999-03-01

申请人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

发明人： Sabine Schoniger ,  Peter Schrogmeier ,  Thomas Hein ,  Stefan Dietrich

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/14

CPC分类号： G11C7/1006 ,  G11C8/00 ,  G11C8/14

摘要： The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.

摘要翻译： 集成存储器具有用于选择相应字节的所有位线的字节选择线以及分配给至少一个字的相应字节的屏蔽信号。 此外，存储器具有列解码器，其具有连接到字选择线的输出，每个字选择线在寻址时都使得如果没有一个屏蔽信号有效则同时选择一个字的所有字节选择线 。 屏蔽信号被激活时，防止寻址字选择线选择分配给相应字节的字节选择线作为相应字。

公开(公告)号：US20090219756A1

公开(公告)日：2009-09-03

申请号：US12039633

申请日：2008-02-28

申请人： Peter Schroegmeier ,  Stefan Dietrich

发明人： Peter Schroegmeier ,  Stefan Dietrich

IPC分类号： G11C11/00

CPC分类号： G11C11/5614 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0061 ,  G11C27/02 ,  G11C2013/0054 ,  G11C2211/5634

摘要： A determination of the memory state of a resistive n-level memory cell is described. The determination includes charging or discharging a read capacity of the memory cell by applying a voltage between a first electrode and a second electrode of the resistive memory cell. A voltage at the second electrode is compared to a reference voltage to obtain a comparison signal. The comparison signal is sampled at, at least, (n−1) time instants during the charge or discharge of the read capacity to obtain sampling values. The memory state of the memory cell can be determined based upon the sampling values.

摘要翻译： 描述了电阻性n级存储单元的存储状态的确定。 确定包括通过在电阻性存储单元的第一电极和第二电极之间施加电压来对存储单元的读取容量进行充电或放电。 将第二电极处的电压与参考电压进行比较以获得比较信号。 在读取容量的充电或放电期间，在至少（n-1）个时刻对比较信号进行采样，以获得采样值。 可以基于采样值来确定存储器单元的存储状态。

公开(公告)号：US07443762B2

公开(公告)日：2008-10-28

申请号：US11593236

申请日：2006-11-06

申请人： Stefan Dietrich

发明人： Stefan Dietrich

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by a WDQS signal and stores write data on the basis of one or more successive write commands. The second FIFO is clocked by an internal clock signal and stores, for a write operation, only addresses associated with valid write data of the write data stored in the first FIFO.

摘要翻译： 一种同步电路，用于处理并同步一个写入操作包含多个写命令的半导体存储器上的写入操作，包括可控的第一FIFO和可控的第二FIFO。 第一个FIFIO由WDQS信号计时，并根据一个或多个连续写入命令存储写入数据。 第二FIFO由内部时钟信号计时，并且对于写入操作仅存储与存储在第一FIFO中的写入数据的有效写入数据相关联的地址。

公开(公告)号：US20080056041A1

公开(公告)日：2008-03-06

申请号：US11469746

申请日：2006-09-01

申请人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

发明人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

IPC分类号： G11C7/02

CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/06 ,  G11C2207/005

摘要： A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

摘要翻译： 存储电路包括连接到多个存储器单元的多个并行位线，连接到位线的多个读出放大器和多个开关，每个开关连接到相应的一对位线， 所述多个位线用于可切换地使相应的一对位线短路。 相应的位线对的位线连接到两个不同的读出放大器，并且相应的位线对的位线与设置在相应的位线之间的位线之间的另一个位线相邻 一对位线。

公开(公告)号：US20080021517A1

公开(公告)日：2008-01-24

申请号：US11778693

申请日：2007-07-17

申请人： Stefan Dietrich

发明人： Stefan Dietrich

IPC分类号： H04R25/00

CPC分类号： H04R25/00 ,  A61N1/36017 ,  A61N1/36036 ,  A61N1/36082 ,  A61N1/361 ,  H04R25/75 ,  H04R2225/021

摘要： The invention relates to an audiological transmission system (1) which is designed to be worn on, in or behind the human ear and has a housing (2), an electrical amplifier (3), a loudspeaker (4) and an output channel (5) for acoustic signals for the ear. In order to advantageously enhance the functionality of such a transmission system, the invention provides for the transmission system (1) to also have a device (6) for transcutaneous stimulation of a nerve of the human body, said device having at least one stimulation electrode (7) and at least one reference electrode (8) for transcutaneous nerve stimulation.

摘要翻译： 本发明涉及一种被设计为佩戴在人耳内或之后的听觉传输系统（1），并且具有外壳（2），电放大器（3），扬声器（4）和输出通道 5）用于耳朵的声学信号。 为了有利地增强这种传输系统的功能，本发明提供了传输系统（1）还具有用于经皮刺激人体神经的装置（6），所述装置具有至少一个刺激电极 （7）和用于经皮神经刺激的至少一个参比电极（8）。

公开(公告)号：US20070245096A1

公开(公告)日：2007-10-18

申请号：US11386176

申请日：2006-03-22

申请人： Stefan Dietrich ,  Rex Kho

发明人： Stefan Dietrich ,  Rex Kho

IPC分类号： G06F13/00

CPC分类号： G06F13/1689 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C15/04

摘要： A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a multiplexer. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for generating information for shifting the FIFO output pointer based on data read from the FIFO cells. The multiplexer is for receiving the value of the FIFO output pointer from the output pointer counter. The multiplexer is also for receiving the multiplexing information for shifting the FIFO output pointer. The multiplexer is further for shifting the value of the FIFO output pointer based on the multiplexing information.

摘要翻译： 存储器包括多个先进先出（FIFO）单元，输出指针计数器，写入训练块和多路复用器。 输出指针计数器用于切换FIFO单元格中FIFO输出指针的值。 写入训练块用于根据从FIFO单元读取的数据产生用于移位FIFO输出指针的信息。 多路复用器用于从输出指针计数器接收FIFO输出指针的值。 复用器还用于接收用于移位FIFO输出指针的复用信息。 复用器还用于基于复用信息来移位FIFO输出指针的值。

公开(公告)号：US07178073B2

公开(公告)日：2007-02-13

申请号：US10389580

申请日：2003-03-14

申请人： Stefan Dietrich ,  Matthias Grewe ,  Peter Mayer ,  Armin Rettenberger

发明人： Stefan Dietrich ,  Matthias Grewe ,  Peter Mayer ,  Armin Rettenberger

IPC分类号： G01C29/00 ,  G11C20/00

CPC分类号： G11C29/12015 ,  G11C29/14

摘要： A method for testing an electronic module having a memory cell device includes writing an information item to the memory cell device at a first clock frequency and then reading-out the information item from the memory cell device at a second clock frequency. The read out information item is reflected at a reflection point and is written back to the memory cell device at the second clock frequency. The reflected information unit is then read-out from the memory cell device with the first clock frequency.

摘要翻译： 一种用于测试具有存储单元设备的电子模块的方法，包括以第一时钟频率将信息项写入存储单元设备，然后以第二时钟频率从存储单元设备读出信息项。 读出的信息项目被反映在反射点处，并以第二时钟频率被写回存储单元装置。 然后，以第一时钟频率从存储单元装置读出反射信息单元。

公开(公告)号：US20060215473A1

公开(公告)日：2006-09-28

申请号：US11372738

申请日：2006-03-10

申请人： Stefan Dietrich

发明人： Stefan Dietrich

IPC分类号： G11C7/00

CPC分类号： G06F11/08 ,  G11C7/1006

摘要： An electric circuit for inverting a data bit of a data burst read out from a memory module comprises a buffer for buffering a data burst being comprised of at least two data words, a decoder device comprised of at least two parallel-connected decoders, each comparing bitwise and simultaneously two neighbouring data words of the data words buffered in the buffer and generating an inversion flag, if the number of different data bits of the two neighbouring data words exceeds half the number of data bits of a data word, a correction device for generating a corrected inversion flag for a specific decoder of the decoders by inverting or not inverting the inversion flag of the specific decoder dependent on the inversion flag generated by the specific decoder and the inversion flags generated by the remaining of the decoders, and an inversion device comprised of a plurality of inverters, each inverting or not inverting a present of the data words of an associated of the decoders dependent on the corrected inversion flag of the associated decoder.

摘要翻译： 用于反相从存储器模块读出的数据脉冲串的数据位的电路包括用于缓冲由至少两个数据字组成的数据脉冲串的缓冲器，由至少两个并联连接的解码器组成的解码器装置，每个比较 如果两个相邻数据字的不同数据位的数量超过数据字的数据位的数量的一半，则缓冲器中缓冲的数据字的两个相邻的数据字并且产生反转标志，校正装置 通过根据由特定解码器产生的反转标志和由剩余的解码器产生的反转标志反转或不反转特定解码器的反转标志来产生解码器的特定解码器的校正反转标志，以及反转装置 由多个反相器组成，每个逆变器反相或不反转依赖于解码器的相关联的数据字的存在 相关解码器的校正反转标志。

公开(公告)号：US20050216623A1

公开(公告)日：2005-09-29

申请号：US11089034

申请日：2005-03-25

申请人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier

发明人： Stefan Dietrich ,  Thomas Hein ,  Peter Schroegmeier

IPC分类号： G06F13/12 ,  G11C11/407 ,  G11C11/4093 ,  H03M9/00

CPC分类号： H03M9/00

摘要： The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.

摘要翻译： 本发明涉及一种用于将并行数据转换为串行数据的并行数据转换器，特别是用于或在DDR半导体存储器中，具有并行存在n个数据信号的至少n个输入端，用于输出串行数据的输出端子 数据信号，连接到输入侧的输入端的可控制锁存器，连接到锁存器的输出并保持最后存在的可控制锁存器的数据信号的公共存储节点，可控旁路装置，其具有 输入，其耦合到输出侧的存储节点并且具有控制终端，通过该输入可以将存在于旁路设备的输入端的可预定状态切换到存储节点。 本发明还涉及具有这种并行 - 串行转换器的半导体存储器以及用于操作这种并行 - 串行转换器的方法。