公开(公告)号：US11658130B2

公开(公告)日：2023-05-23

申请号：US17138981

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Osvaldo Jorge Lopez ,  Lance Cole Wright

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49575

Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.

公开(公告)号：US11177197B2

公开(公告)日：2021-11-16

申请号：US16581971

申请日：2019-09-25

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Lance Cole Wright ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a leadframe including a die pad and a plurality of lead terminals. A vertical semiconductor device is attached on a first side by a die attach material to the die pad. A first clip is on the first vertical device that is solder connected to a terminal of the first vertical device on a second side opposite to the first side providing a first solder bonded interface, wherein the first clip is connected to at least a first of the lead terminals. The first solder bonded interface includes a first protruding surface standoff therein that extends from a surface on the second side of the first vertical device to physically contact the first clip.

公开(公告)号：US20200258822A1

公开(公告)日：2020-08-13

申请号：US16274562

申请日：2019-02-13

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Tianyi Luo ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A method of making a semiconductor device includes separating a conductive structure of a leadframe into interior conductive leads using an etching process. The method includes forming a first molded structure by applying a first molding compound to a leadframe having a conductive structure, separating the conductive structure into at least two interior contact portions, attaching a semiconductor die to at least one of the interior contact portions, the at least two interior contact portions being supported by the first molding compound, and forming a second molded structure by applying a second molding compound to at least part of the semiconductor die and at least two interior contact portions.

公开(公告)号：US10153220B2

公开(公告)日：2018-12-11

申请号：US15785778

申请日：2017-10-17

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L23/057 ,  H01L23/08 ,  H01L25/16 ,  H01L25/04 ,  H01L21/48 ,  H01L25/00 ,  H01L21/78 ,  H01L23/13

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

公开(公告)号：US10121716B2

公开(公告)日：2018-11-06

申请号：US15634232

申请日：2017-06-27

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L21/52 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/00 ,  H01L23/373

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

公开(公告)号：US10109614B2

公开(公告)日：2018-10-23

申请号：US15053089

申请日：2016-02-25

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/065 ,  H01L23/06 ,  H01L25/18 ,  H01L25/00 ,  H01L23/053 ,  H01L23/00 ,  H01L21/50 ,  H01L23/13 ,  H01L23/14 ,  H01L29/06 ,  H01L23/498

Abstract: An electronic system comprises a first chip of single-crystalline semiconductor shaped as a hexahedron and including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by retaining walls, and including a second electronic device. The container shaped as a slab bordered by the retaining walls and including conductive traces and terminals. The first chip is attached to the slab of second chip, forming nested chips. The first and second chips embedded in the container. The nested first and second chips are operable as an electronic system and the container is operable as the package of the system.

公开(公告)号：US20180096978A1

公开(公告)日：2018-04-05

申请号：US15820246

申请日：2017-11-21

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L25/00 ,  H01L27/088 ,  H01L27/082 ,  H01L31/18 ,  H01L31/042 ,  H01L31/028 ,  H01L31/0216 ,  H01L31/02

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20180040527A1

公开(公告)日：2018-02-08

申请号：US15785778

申请日：2017-10-17

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L21/48 ,  H01L25/16 ,  H01L25/00 ,  H01L21/78 ,  H01L23/13

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/78 ,  H01L23/057 ,  H01L23/08 ,  H01L23/13 ,  H01L25/16 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (I-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

公开(公告)号：US20170301595A1

公开(公告)日：2017-10-19

申请号：US15634232

申请日：2017-06-27

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L23/13 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/3738 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/15153 ,  H01L2924/157

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

公开(公告)号：US20170229435A1

公开(公告)日：2017-08-10

申请号：US15019275

申请日：2016-02-09

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Haian Lin

IPC: H01L25/16 ,  H01L27/088 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73251 ,  H01L2224/80001 ,  H01L2224/9222 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/1425 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H02M3/155 ,  H02M3/158 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.