公开(公告)号：US20160268505A1

公开(公告)日：2016-09-15

申请号：US14645878

申请日：2015-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting Sung ,  Chang-Ming Wu ,  Hsai-Wei Chen ,  Shih-Chang Liu ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.

Abstract translation: 本公开涉及具有RRAM单元的集成电路器件和相关联的形成方法。 在一些实施例中，集成电路器件具有由下部ILD层围绕的下部金属互连层和设置在下部金属互连层上的底部电极。 底部电极具有被底部电介质层包围的下部和比下部更宽的上部。 底部介电层设置在下部金属互连层和下部ILD层之上。 集成电路器件还具有位于底部电极上的可变电阻的RRAM电介质，以及位于RRAM电介质上方的顶部电极。 集成电路器件还具有位于底部电介质层上方的顶部电介质层，该电介质层邻接底部电极的上部，RRAM电介质和顶部电极的侧壁。

公开(公告)号：US20160204118A1

公开(公告)日：2016-07-14

申请号：US14596340

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yung-Chang Chang

IPC: H01L27/115 ,  H01L29/423 ,  H01L23/528 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/265 ,  H01L21/768 ,  H01L29/788 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

Abstract translation: 本公开的一些实施例涉及闪存设备。 闪存器件包括在半导体衬底内间隔开的第一和第二个源/漏（S / D）区域。 公共S / D区域横向地布置在第一和第二单独S / D区域之间，并且通过第一沟道区域与第一单独S / D区域分离，并且与第二个别S / D区域分开第二个 渠道区域。 擦除门被布置在公共S / D上。 浮置栅极设置在第一沟道区上方并且布置在擦除栅极的第一侧。 控制栅极设置在浮动栅极上。 字线布置在第一通道区域上方，并通过浮动栅极和控制栅极与擦除栅极间隔开。 字线的上表面是凹面。

公开(公告)号：US20160087056A1

公开(公告)日：2016-03-24

申请号：US14493538

申请日：2014-09-23

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Chang-Ming Wu ,  Tsung-Hsueh Yang ,  Sheng-Chieh Chen ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.

Abstract translation: 一些实施例涉及具有不对称浮动门几何形状的存储器件。 控制门布置在浮动门上。 擦除栅极横向布置在浮动栅极附近，并且通过隧道电介质层与浮动栅极分离。 侧壁间隔件沿着控制栅极的垂直侧壁并且在浮动栅极的上表面上方布置。 浮动门上表面的一部分形成水平延伸通过侧壁间隔物的“凸缘”或尖角。 浮动栅极的侧壁形成凹入表面，其从凸缘向下朝向浮动门内的颈部区域逐渐变细。 与具有平面侧壁表面的浮动栅极相比，该凸缘提供了更快的隧道隧道隧穿隧道介电层的路径。 因此，该凸起因此提高了存储器件的擦除速度。

公开(公告)号：US20160064656A1

公开(公告)日：2016-03-03

申请号：US14471082

申请日：2014-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-ken Lin ,  Chang-Ming Wu ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/1675

Abstract: A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.

Abstract translation: 提供了具有通过空腔与PCM单元的横向周围区域电隔离的加热元件的相变存储器（PCM）单元。 电介质区域布置在第一和第二导体之间。 在穿过介电区延伸到第一导体的孔内布置加热塞。 加热插头包括沿着孔的侧壁延伸的加热元件，并且包括侧壁结构，该侧壁结构包括布置在加热元件和侧壁之间的空腔。 相变元件与加热塞热连通并且布置在加热塞和第二导体之间。 还提供了用于制造PCM单元的方法。

公开(公告)号：US20150380568A1

公开(公告)日：2015-12-31

申请号：US14316864

申请日：2014-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed. A charge trapping dielectric layer is formed conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates, and a pair of memory gates corresponding to the pair of select gates is formed over and laterally abutting the charge trapping dielectric layer. The resulting semiconductor structure is also provided.

Abstract translation: 提供了一对制造分离栅闪存单元的半导体结构的方法。 形成在半导体衬底上间隔开的一对选择栅极，并且形成填充选择栅极之间的中心区域的牺牲隔离物。 电荷捕获电介质层沿着选择栅极的侧壁和牺牲间隔物和选择栅极的顶表面保形地形成，并且对应于该对选择栅极的一对存储栅极形成在电荷捕获电介质上方并横向邻接 层。 还提供所得的半导体结构。

公开(公告)号：US20150372136A1

公开(公告)日：2015-12-24

申请号：US14310277

申请日：2014-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/0847 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7831 ,  H01L29/792

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 第一和第二源极/漏极区域之间形成沟道区域。 半导体结构还包括选择栅极和在沟道区域上的第一和第二源极/漏极区域间隔开的存储栅极。 选择栅极延伸在沟道区上方并且终止于具有沿着沿着选择栅极的长度延伸的轴线的不对称的顶表面的线端，并且平分选择栅极的宽度。 更重要的是，半导体结构包括布置在存储器栅极和选择栅极的相邻侧壁之间并且布置在存储器栅极下方的电荷捕获电介质。 还提供了制造半导体结构的方法。

公开(公告)号：US20150372121A1

公开(公告)日：2015-12-24

申请号：US14308872

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7883

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括具有源极区和漏极区的半导体衬底。 此外，半导体结构包括在源极和漏极区域之间间隔开半导体衬底的浮置栅极，字线和擦除栅极，其中浮置栅极布置在字线和擦除栅极之间。 半导体结构还包括设置在字线和浮置栅极之间的第一电介质侧壁区域以及设置在擦除栅极和浮置栅极之间的第二电介质侧壁区域。 第一电介质侧壁区域的厚度大于第二电介质侧壁区域的厚度。 还提供了制造半导体结构的方法和包括半导体结构的集成电路。

公开(公告)号：US20150333173A1

公开(公告)日：2015-11-19

申请号：US14276340

申请日：2014-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device.

Abstract translation: 本公开的一些实施例涉及一种存储器件，其包括形成在衬底的沟道区上的浮置栅极和形成在浮置栅极上的控制栅极。 第一和第二间隔件沿着控制栅极的侧壁形成，并且在浮动栅极的外边缘上延伸以形成不均匀的悬垂，这可以引起存储器件的擦除速度的广泛分布。 为了提高擦除速度分布，在擦除栅极形成之前，对第一和第二间隔物进行蚀刻处理。 蚀刻工艺去除第一和第二间隔件的底部区域与浮动栅极的顶部区域之间的界面处的第一和第二间隔物的突出部分，以在界面处形成平坦表面，并且改善了擦拭速度分布 存储设备。

公开(公告)号：US20150236030A1

公开(公告)日：2015-08-20

申请号：US14182952

申请日：2014-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them.

Abstract translation: 本公开涉及一种分裂门存储器件，其需要比传统的基线工艺更少数量的处理步骤及其制造方法。 字栅/选择栅极（SG）对围绕牺牲间隔物形成。 所得到的SG结构具有可区分的非平面顶表面。 覆盖选择栅的间隔层也遵循SG顶表面的形状。 设置在栅极间介电层上方并且布置在每个存储器栅极和选择栅极的相邻侧壁之间的电介质在它们之间提供隔离。

公开(公告)号：US11348935B2

公开(公告)日：2022-05-31

申请号：US16869780

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.