公开(公告)号：US10103146B2

公开(公告)日：2018-10-16

申请号：US15838451

申请日：2017-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/148 ,  H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

Abstract: A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.

公开(公告)号：US20180175175A1

公开(公告)日：2018-06-21

申请号：US15653720

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20180166442A1

公开(公告)日：2018-06-14

申请号：US15838451

申请日：2017-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Cheng-Yu Yang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847

Abstract: A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET device also includes a plurality of gate structures that partially wrap around the fin structures. The fin structures each extend in a first direction, and the gate structures each extend in a second direction different from the first direction. An epitaxial structure is formed over at least a side surface of each of the fin structures. The epitaxial structure includes: a first epi-layer, a second epi-layer, or a third epi-layer. The epitaxial structure formed over each fin structure is separated from adjacent epitaxial structures by a gap. A silicide layer is formed over each of the epitaxial structures. The silicide layer at least partially fills in the gap. Conductive contacts are formed over the silicide layer.

公开(公告)号：US20250169159A1

公开(公告)日：2025-05-22

申请号：US19029882

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Chia-Ta Yu ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Feng-Cheng Yang

IPC: H10D84/01 ,  H10D30/01 ,  H10D30/62 ,  H10D84/03 ,  H10D84/85

Abstract: A semiconductor device includes a substrate, an isolation feature disposed on the substrate, first and second fins protruding from the substrate and upwardly through the isolation feature, and a gate stack engaging each of the fins. The semiconductor device also includes a first epitaxial layer having a first portion over top and sidewall surfaces of S/D regions of the first fin and a second portion over top and sidewall surfaces of S/D regions of the second fin, a second epitaxial layer having a first portion over top and sidewall surfaces of the first portion of the first epitaxial layer and a second portion over top and sidewall surfaces of the second portion of the first epitaxial layer. The first and second portions of the second epitaxial layer are spaced apart. Each of the first and second portions of the second epitaxial layer is in physical contact with the isolation feature.

公开(公告)号：US12266576B2

公开(公告)日：2025-04-01

申请号：US17813086

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105

Abstract: A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

公开(公告)号：US20240387731A1

公开(公告)日：2024-11-21

申请号：US18784144

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Jyun-Chih Lin ,  Tzu-Hsiang Hsu ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

公开(公告)号：US12148505B2

公开(公告)日：2024-11-19

申请号：US18362685

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L21/822 ,  H10B51/20 ,  H10B99/00

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US12136658B2

公开(公告)日：2024-11-05

申请号：US18349448

申请日：2023-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

公开(公告)号：US20240332084A1

公开(公告)日：2024-10-03

申请号：US18738707

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

Abstract: A method includes providing a workpiece including a gate structure (MG), a first spacer along a sidewall of the MG, a second spacer along a sidewall of the first spacer, and a source/drain (S/D) feature adjacent to the second spacer. The method further includes forming a contact trench over the S/D feature, removing the second spacer to form an air gap between the MG and the S/D feature, depositing a first dielectric layer over the S/D feature and partially filling the air gap, removing a portion of the first dielectric layer to expose a central portion of a top surface of the S/D feature while a side portion of the top surface of the S/D feature remains under the first dielectric layer, forming an S/D contact in the contact trench, removing the first dielectric layer to extend the air gap, and depositing a second dielectric layer over the air gap.

公开(公告)号：US12068389B2

公开(公告)日：2024-08-20

申请号：US18300192

申请日：2023-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/311 ,  H01L21/764 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/764 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.