公开(公告)号：US20250117224A1

公开(公告)日：2025-04-10

申请号：US18981824

申请日：2024-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

公开(公告)号：US12260219B2

公开(公告)日：2025-03-25

申请号：US18355939

申请日：2023-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Timothy D. Anderson ,  Paul Gauvreau

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

公开(公告)号：US12072824B2

公开(公告)日：2024-08-27

申请号：US17030518

申请日：2020-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David M. Thompson ,  Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Abhijeet A Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/40 ,  G06F13/364 ,  G06F13/42 ,  H04L12/801 ,  H04L12/819 ,  H04L47/10 ,  H04L47/215

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

公开(公告)号：US11972236B1

公开(公告)日：2024-04-30

申请号：US17942239

申请日：2022-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L Davis

IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

CPC classification number: G06F8/433 ,  G06F5/06 ,  G06F9/30065

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

公开(公告)号：US11853225B2

公开(公告)日：2023-12-26

申请号：US17068730

申请日：2020-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Raymond Michael Zbiciak ,  Kai Chirca ,  Daniel Brad Wu

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/0862 ,  G06F12/1009 ,  G06F9/48 ,  G06F9/46 ,  G06F12/0891 ,  H03M13/15 ,  G06F12/0882

CPC classification number: G06F12/1027 ,  G06F9/467 ,  G06F9/4881 ,  G06F12/0862 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/1009 ,  H03M13/1575 ,  G06F2212/1021 ,  G06F2212/602 ,  G06F2212/68

Abstract: A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.

公开(公告)号：US20230367717A1

公开(公告)日：2023-11-16

申请号：US18357748

申请日：2023-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/38 ,  G06F13/16

CPC classification number: G06F12/0875 ,  G06F9/30047 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/383 ,  G06F13/1668 ,  G06F12/0811

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

公开(公告)号：US11709778B2

公开(公告)日：2023-07-25

申请号：US16916254

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson

IPC: G06F9/38 ,  G06F12/0802 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F12/0897 ,  G06F13/16 ,  G06F12/0811 ,  G06F12/10

CPC classification number: G06F12/0875 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0897 ,  G06F13/1668 ,  G06F12/0811 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

公开(公告)号：US11693661B2

公开(公告)日：2023-07-04

申请号：US17241198

申请日：2021-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Kai Chirca

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/3822 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60

Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, beginning execution of the first instruction, receiving one or more second instructions for execution on the instruction execution pipeline, the one or more second instructions associated with a higher priority task than the first instruction, storing a register state associated with the execution of the first instruction in one or more registers of a capture queue associated with the instruction execution pipeline, copying the register state from the capture queue to a memory, determining that the one or more second instructions have been executed, copying the register state from the memory to the one or more registers of the capture queue, and restoring the register state to the instruction execution pipeline from the capture queue.

公开(公告)号：US20230185649A1

公开(公告)日：2023-06-15

申请号：US18164688

申请日：2023-02-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy D. Anderson ,  Duc Bui ,  Kai Chirca

IPC: G06F11/07 ,  G06F11/30 ,  G06F12/0875 ,  G06F12/0862 ,  G06F11/27 ,  G06F13/16 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/36

CPC classification number: G06F11/0772 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3867 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F11/00 ,  G06F11/27 ,  G06F11/073 ,  G06F11/0721 ,  G06F11/3037 ,  G06F11/3648 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1673 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/602

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

公开(公告)号：US11614940B2

公开(公告)日：2023-03-28

申请号：US17215013

申请日：2021-03-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.