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    Method for fabricating dielectric mixed layers and capacitive element and use thereof
    52.
    发明申请
    Method for fabricating dielectric mixed layers and capacitive element and use thereof 有权
    电介质混合层和电容元件的制造方法及其应用

    公开(公告)号：US20050258510A1

    公开(公告)日：2005-11-24

    申请号：US11125654

    申请日：2005-05-10

    申请人： Martin Gutsche ,  Harald Seidl

    发明人： Martin Gutsche ,  Harald Seidl

    IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/08 ,  H01L29/76

    CPC分类号： H01L28/56 ,  H01L21/022 ,  H01L21/31604 ,  H01L21/31608 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

    摘要： The present invention provides a method for fabricating a capacitive element (100), a substrate (101) being provided as a first electrode layer of the capacitive element (100), the substrate (101) provided as an electrode layer is conditioned, a dielectric layer (102) is deposited on the conditioned substrate (101) and a second electrode layer (104) is applied on the layer stack produced, the layer stack being modified by a heat treatment in such a way that the dielectric layer (102) deposited on the conditioned substrate (101) forms a dielectric mixed layer (105) with a reaction layer (103) deposited on the dielectric layer (102), which dielectric mixed layer has an increased dielectric constant (k) or an increased thermal stability.

    摘要翻译： 本发明提供一种电容元件（100）的制造方法，设置有作为电容元件（100）的第一电极层的基板（101），将作为电极层设置的基板（101）进行调理， 层（102）沉积在经调理的基底（101）上，并且第二电极层（104）被施加在所产生的层叠层上，通过热处理改变层堆叠，使得介电层（102）沉积 在调理衬底（101）上形成电介质混合层（105），其上沉积有介电层（102）上的反应层（103），该电介质混合层具有增加的介电常数（k）或增加的热稳定性。

    Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell
    55.
    发明申请
    Method for fabricating a trench capacitor having an insulation collar, which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell 失效
    一种用于制造具有绝缘套环的沟槽电容器的方法，所述绝缘套环通过埋入触点电连接到一侧的衬底，特别是用于半导体存储器单元

    公开(公告)号：US20050070066A1

    公开(公告)日：2005-03-31

    申请号：US10935520

    申请日：2004-09-07

    申请人： Martin Gutsche ,  Harald Seidl

    发明人： Martin Gutsche ,  Harald Seidl

    IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/334 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181

    摘要： The present invention provides a method for fabricating a trench capacitor having an insulation collar (10; 10a, 10b) in a substrate (1), which is electrically connected to the substrate (1) on one side via a buried contact (15a, 15b), in particular for a semiconductor memory cell having a planar select transistor which is provided in the substrate (1) and is connected via the buried contact (15a, 15b), comprising the steps of: providing a trench (5) in the substrate (1) using a hard mask (2, 3) with a corresponding mask opening; providing a capacitor dielectric (30) in the lower and middle regions of the trench, the insulation collar (10) in the middle and upper regions of the trench and an electrically conductive filling (20) at least up to the top side of the insulation collar (10); completely filling the trench (5) with a filling material (50; 50′; 50″; 20); carrying out an STI trench production process; removing the filling material (50; 50′; 50″; 20) and lowering the electrically conductive filling (20) to below the top side of the insulation collar (10); forming an insulation region (IS; IS1, IS2) on one side with respect to the substrate (1) above the insulation collar (10); uncovering a connection region (KS; KS1, KS2) on the other side with respect to the substrate (1) above the insulation collar (10); and forming the buried contact (15a, 15b) by depositing and etching back a C filling (70; 70′; 70″; 70′″).

    摘要翻译： 本发明提供一种在衬底（1）中具有绝缘套环（10; 10a，10b）的沟槽电容器的制造方法，该沟槽电容器在一侧通过埋入触点（15a，15b）电连接到衬底 ），特别是具有设置在基板（1）中并通过埋入触点（15a，15b）连接的平面选择晶体管的半导体存储单元，包括以下步骤：在基板中提供沟槽（5） （1）使用具有相应掩模开口的硬掩模（2,3）; 在所述沟槽的下部和中部区域中提供电容器电介质（30），所述沟槽的中部和上部区域中的所述绝缘环（10）和至少直到所述绝缘体的顶侧的导电填料（20） 衣领（10）; 用填充材料（50; 50'; 50“; 20）完全填充沟槽（5）; 开展STI沟槽生产工艺; 去除所述填充材料（50; 50'; 50“; 20）并将所述导电填料（20）降低到所述绝缘套环（10）的顶侧下方; 在所述绝缘套环（10）上方相对于所述基板（1）在一侧上形成绝缘区域（IS; IS1，IS2）; 在绝缘套环（10）上方相对于衬底（1）露出另一侧的连接区域（KS; KS1，KS2）; 以及通过沉积和蚀刻C填充物（70; 70'; 70“; 70”'）来形成所述埋入触点（15a，15b）。

    Memory cell with a stacked capacitor
    59.
    发明授权
    Memory cell with a stacked capacitor 有权

    公开(公告)号：US06437387B1

    公开(公告)日：2002-08-20

    申请号：US09774743

    申请日：2001-01-31

    申请人： Martin Gutsche

    发明人： Martin Gutsche

    IPC分类号： H01L27108

    摘要： A semiconductor memory cell includes a field effect transistor coupled to a storage capacitor that formed as a multilayer stack over the surface of the silicon chip of the cell. The capacitor is formed by three conformal layers over the surface of a cup-shaped contact hole in a silicon oxide layer overlying the surface of the chip.

    Method for forming metallization in semiconductor devices with a self-planarizing material
    60.
    发明授权
    Method for forming metallization in semiconductor devices with a self-planarizing material 失效
    在具有自平面化材料的半导体器件中形成金属化的方法

    公开(公告)号：US5854126A

    公开(公告)日：1998-12-29

    申请号：US829257

    申请日：1997-03-31

    申请人： Dirk Tobben ,  Bruno Spuler ,  Martin Gutsche ,  Peter Weigand

    发明人： Dirk Tobben ,  Bruno Spuler ,  Martin Gutsche ,  Peter Weigand

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/12 ,  H05K1/00 ,  H05K3/06 ,  H05K3/22 ,  H05K3/24 ,  H01L21/469 ,  H01L21/312

    CPC分类号： H05K3/061 ,  H01L21/32139 ,  H01L21/76838 ,  H05K1/0284 ,  H05K2201/09018 ,  H05K2203/0585

    摘要： A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer. The second mask is used to etch grooves in the relatively non-planar conductive metal layer and thereby form the plurality of electrically conductive wires in the metal layer. The wires are separated from each other by the grooves formed in the relatively non-planar metal layer. The planarization layer is formed by a spinning-on an organic polymer, for example an organic polymer having silicon, or a flowable oxide, or a hydrogensilsequioxane, or divinyl-siloxane-benzocyclobutene. The metal layer is etched using reactive ion etching. The planarization layer is removed using a wet chemical etch.

    摘要翻译： 一种在基板上形成多根导电线的方法。 该方法包括在衬底的表面上形成相对非平面的金属层。 自平面化材料沉积在金属层上。 自平面化材料在金属层的表面上形成平坦化层。 与相对非平面的金属层相比，平坦化层具有相对平坦的表面。 在平坦化层的表面上沉积光致抗蚀剂层。 用多个凹槽对光致抗蚀剂层进行图案化以形成掩模，该掩模具有暴露平坦化层的下部的这种凹槽。 光致抗蚀剂掩模用作掩模以蚀刻平坦化层的暴露部分中的凹槽，从而形成第二掩模。 第二掩模暴露相对非平面金属层的下层部分。 第二掩模用于蚀刻相对非平面导电金属层中的凹槽，从而在金属层中形成多个导电线。 电线通过在相对非平面的金属层中形成的凹槽彼此分离。 平坦化层是通过旋涂有机聚合物，例如具有硅的有机聚合物，或可流动的氧化物，或氢化二烷基锡，或二乙烯基 - 硅氧烷 - 苯并环丁烯等形成的。 使用反应离子蚀刻蚀刻金属层。 使用湿化学蚀刻去除平坦化层。