公开(公告)号：US07800131B2

公开(公告)日：2010-09-21

申请号：US11921857

申请日：2006-06-12

申请人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

发明人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/404 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/802 ,  H01L29/812

摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.

摘要翻译： 场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极 （118）。 第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。 当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠 （113）表示为Lol，栅极长度为Lg，表示为0＆nlE; Lol / Lg＆nlE; 1的关系成立。

公开(公告)号：US20090230429A1

公开(公告)日：2009-09-17

申请号：US11921854

申请日：2006-06-12

申请人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tasuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

发明人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tasuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/802 ,  H01L29/812

摘要： A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.

摘要翻译： 在高电压运行和高频下表现出良好性能的场效应晶体管（100）包括第一场极板电极（116）和第二场板电极（118）。 第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。 当在栅极长度方向的横截面视图中，第二场板电极（118）与包括第一场极板电极和栅电极的结构的上部重叠的重叠区域的栅极长度方向上的长度（ 113）被指定为Lol，栅极长度为Lg，表示为0 <= Lol / Lg <= 1的关系成立。

公开(公告)号：US20090173968A1

公开(公告)日：2009-07-09

申请号：US12097700

申请日：2006-12-12

申请人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

发明人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

IPC分类号： H01L29/205

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a drain electrode 103 provided on the undoped GaN layer 107 as being spaced from each other, a recess 111 provided in the region between the source electrode 101 and the drain electrode 103, as being extended through the undoped GaN layer 107, a gate electrode 102 buried in the recess 111 as being brought into contact with the AlGaN electron donor layer 106 on the bottom surface thereof, and an SiN film 108 provided on the undoped GaN layer 107, in the region between the gate electrode 102 and the drain electrode 103.

摘要翻译： 半导体器件100包含未掺杂的GaN沟道层105，设置在与其接触的未掺杂的GaN沟道层105上的AlGaN电子供体层106，设置在AlGaN电子供体层106上的未掺杂的GaN层107，源电极 101和设置在未掺杂的GaN层107上彼此间隔开的漏电极103，设置在源电极101和漏电极103之间的区域中的凹槽111延伸穿过未掺杂的GaN层107，栅极 埋入凹槽111中的电极102与其底表面上的AlGaN电子供体层106接触，以及设置在未掺杂的GaN层107上的SiN膜108，在栅电极102和漏极之间的区域 103。

公开(公告)号：US07459788B2

公开(公告)日：2008-12-02

申请号：US10590730

申请日：2005-02-28

申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Masaaki Kuzuhara ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Koji Hataya

发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Masaaki Kuzuhara ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Koji Hataya

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L33/40 ,  H01L33/32

摘要： An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first metal film is composed of at least one material selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta and Zr. The second metal film is composed of at least one material different from that of the first metal film (102), selected from a group consisting of V, Mo, Ti, Nb, W, Fe, Hf, Re, Ta, Zr, Pt and Au.

摘要翻译： 具有氮化物半导体的氮化物半导体器件的欧姆电极结构。 欧姆电极结构设置有形成在氮化物半导体上的第一金属膜和形成在第一金属膜上的第二金属膜。 第一金属膜由选自V，Mo，Ti，Nb，W，Fe，Hf，Re，Ta和Zr中的至少一种材料构成。 第二金属膜由与V，Mo，Ti，Nb，W，Fe，Hf，Re，Ta，Zr，Pt等组成的组中的至少一种不同于第一金属膜的材料构成 和Au。

公开(公告)号：US20070158692A1

公开(公告)日：2007-07-12

申请号：US11571290

申请日：2005-06-24

申请人： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Ando ,  Masaaki Kuzuhara ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Koji Hataya

发明人： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Ando ,  Masaaki Kuzuhara ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Koji Hataya

IPC分类号： H01L29/76

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/78

摘要： The present invention provides a semiconductor device capable of suppressing current collapse, and also of preventing dielectric breakdown voltage and gain from lowering so as to perform high-voltage operation and realize an ideal high output. On a substrate (101), there are formed a buffer layer (102) made of a first GaN-based semiconductor, a carrier traveling layer (103) made of a second GaN-based semiconductor and a carrier supplying layer (104) made of a third GaN-based semiconductor. A recess structure (108) is made by eliminating a part of a first insulation film (107) and a part of the carrier supplying layer (104). Next, a gate insulation film (109) is deposited, and then a gate electrode (110) is formed so as to fill up the recess portion (108) and cover on over an area where the first insulation film (107) remains so that its portion on the drain electrode side is longer than that on the source electrode side. Such a recess structure is employed so as to provide the high-output semiconductor device capable of performing the high-voltage operation.

摘要翻译： 本发明提供一种能够抑制电流塌陷以及防止电介质击穿电压和增益降低的半导体器件，从而进行高压操作并实现理想的高输出。 在基板（101）上形成有由第一GaN基半导体构成的缓冲层（102），由第二GaN基半导体构成的载流子移动层（103）和由 第三GaN基半导体。 通过消除第一绝缘膜（107）的一部分和载体供给层（104）的一部分来制造凹陷结构（108）。 接下来，沉积栅极绝缘膜（109），然后形成栅电极（110），以填充凹部（108）并覆盖在第一绝缘膜（107）保留的区域上，使得 其漏电极侧的部分比源电极侧的部分长。 采用这样的凹部结构来提供能够执行高电压操作的高输出半导体器件。

公开(公告)号：US08981434B2

公开(公告)日：2015-03-17

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/76 ,  H01L29/812 ,  H01L29/201 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

公开(公告)号：US08674409B2

公开(公告)日：2014-03-18

申请号：US13141449

申请日：2009-12-25

申请人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

发明人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66462

摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.

摘要翻译： 提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。 在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结 如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度 具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

公开(公告)号：US08476756B2

公开(公告)日：2013-07-02

申请号：US13137927

申请日：2011-09-21

申请人： Naotaka Kuroda ,  Akio Wakejima ,  Masahiro Tanomura ,  Hironobu Miyamoto

发明人： Naotaka Kuroda ,  Akio Wakejima ,  Masahiro Tanomura ,  Hironobu Miyamoto

IPC分类号： H01L23/34 ,  H01L23/10

CPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2223/6644 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy≧K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz≧K2yy>K2xx or K2yy≧K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.

摘要翻译： 半导体器件包括具有矩形二维几何形状并用作热源的半导体元件，包括安装在其上的半导体元件的第一散热部分和与第一散热部分相对的一侧连接的第二散热部分 其包括半导体元件。 导热方向分量之间的关系为K1yy> = K1xx> K1zz，其中X，Y和Z方向上的散热器部分的三维热导率的方向分量被确定为Kxx，Kyy和Kzz。 第二散热器部分的热导率的方向分量之间的关系是K2zz> = K2yy> K2xx或K2yy> = K2zz> K2xx，其中X，Y和Y中的第二散热器部分的热导率的方向分量 X方向确定为K2xx，K2yy和K2zz。

公开(公告)号：US20130037868A1

公开(公告)日：2013-02-14

申请号：US13548078

申请日：2012-07-12

申请人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

发明人： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

摘要： A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization. In other words, the intensities of polarization of the semiconductor layers change with an inclination based on their distances from the gate electrode so that, at each interface between two semiconductor layers, the amount of negative charge becomes larger than that of positive charge.

摘要翻译： 半导体器件包括：第一氮化物半导体层; 形成在第一氮化物半导体层上的第二氮化物半导体层; 以及经由栅极绝缘膜与第二氮化物半导体层相对的栅电极。 由于第二氮化物半导体层通过堆叠其Al组成比彼此不同的多个半导体层而形成，所以第二氮化物半导体层的Al组成比逐步变化。 形成第二氮化物半导体层的半导体层在相同的方向上极化，使得在半导体层中，更靠近栅电极的半导体层具有较高（或更低）的极化强度。 换句话说，半导体层的极化强度随着与栅电极的距离的倾斜而变化，使得在两个半导体层之间的每个界面处，负电荷的量变得大于正电荷的量。

公开(公告)号：US20120199889A1

公开(公告)日：2012-08-09

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/78

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased.A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。