公开(公告)号：US06366490B1

公开(公告)日：2002-04-02

申请号：US09879054

申请日：2001-06-13

申请人： Yoshiaki Takeuchi ,  Yukihito Oowaki

发明人： Yoshiaki Takeuchi ,  Yukihito Oowaki

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： This invention is such that, in a series-connected TC parallel-unit type ferroelectric RAM composed of a series connection of a plurality of unit cells, each unit cell being such that a ferroelectric capacitor is connected between the source and drain of a cell transistor, for instance, plate electrode wires are provided in the longitudinal direction of bit line pairs. The plate electrode wires are shared in memory block groups, each group being a set of a plurality of memory cell blocks connected to the same bit line pair. This causes only the memory cells read from or written into to be accessed by the selected word line and selected plate electrode wire in one select operation.

摘要翻译： 本发明使得在由多个单元电池的串联连接构成的串联连接的TC并联单元型铁电RAM中，每个单电池使得在单电池晶体管的源极和漏极之间连接有铁电电容器 例如，在位线对的长度方向上设置平板电极线。 板电极线在存储块组中共享，每组是连接到同一位线对的多个存储单元块的集合。 这将导致在一个选择操作中，所选择的字线和选定的板电极线只能读取或写入存储单元。

公开(公告)号：US06349395B2

公开(公告)日：2002-02-19

申请号：US09154027

申请日：1998-09-16

申请人： Kazunori Ohuchi ,  Masako Yoshida ,  Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

发明人： Kazunori Ohuchi ,  Masako Yoshida ,  Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.

摘要翻译： 集成电路具有可配置逻辑块，其是可重新配置的，执行固定操作的硬连线逻辑块，以及存储器。 存储器存储用于配置可配置逻辑块的配置数据，用于确定可配置逻辑块和硬连线逻辑块之间的连接的块连接数据，以及用于确定部分电路之间的连接的部分电路连接数据，每个部分电路由选择的逻辑块组成 在可配置和硬连线的逻辑块之间。 这些数据由逻辑块共享，以减少集成电路中的存储器数量并提高集成电路的封装密度。

公开(公告)号：US6124744A

公开(公告)日：2000-09-26

申请号：US824743

申请日：1997-03-26

申请人： Yukihito Oowaki

发明人： Yukihito Oowaki

IPC分类号： G06F1/10 ,  H03K5/13 ,  H03K5/14

CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K5/14

摘要： The present invention relates to, more specifically, an electronic circuit apparatus having a main system portion and a subsystem portion connected to the main system portion. In the electronic circuit apparatus, at least either the main system or the subsystem comprises a clock source, a clock wire having an outgoing path and an incoming path, wherein a clock signal from the clock source is inputted from one end of the outgoing path, and at least one receiver connected to an optional position of the outgoing path, further connected to a position of the outgoing path adjacent to the optional position, for supplying a clock signal having an optional delay level relative to the clock signal from the clock source according to a delay level between each clock signal at the positions.

摘要翻译： 本发明更具体地涉及具有连接到主系统部分的主系统部分和子系统部分的电子电路装置。 在电子电路装置中，主系统或子系统中的至少一个包括时钟源，具有输出路径的时钟线和输入路径，其中来自时钟源的时钟信号从输出路径的一端输入， 以及连接到输出路径的可选位置的至少一个接收器，进一步连接到与可选位置相邻的输出路径的位置，以提供相对于来自时钟源的时钟信号具有可选延迟电平的时钟信号，根据 到位置处的每个时钟信号之间的延迟水平。

公开(公告)号：US6112163A

公开(公告)日：2000-08-29

申请号：US38373

申请日：1998-03-11

申请人： Yukihito Oowaki ,  Masatoshi Sekine ,  Hiroshige Fujii

发明人： Yukihito Oowaki ,  Masatoshi Sekine ,  Hiroshige Fujii

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G01R15/12

CPC分类号： G01R31/318566

摘要： A reconfigurable circuit is reconstructed to three or more operating circuit blocks. Upon testing, the same data is inputted to each of the reconstructed operating circuit blocks. A majority circuit formed in the reconfigurable circuit compares results of operations of the operating circuit blocks and outputs information indicating which of the operating circuit blocks is in trouble.

摘要翻译： 可重构电路被重建为三个或更多个操作电路块。 在测试时，将相同的数据输入到每个重建的操作电路块。 形成在可重构电路中的多数电路比较了操作电路块的操作结果并输出指示哪些操作电路块处于故障状态的信息。

公开(公告)号：US6087893A

公开(公告)日：2000-07-11

申请号：US956956

申请日：1997-10-23

申请人： Yukihito Oowaki ,  Tsuneaki Fuse

发明人： Yukihito Oowaki ,  Tsuneaki Fuse

IPC分类号： H01L27/092 ,  G05F1/46 ,  G05F3/02 ,  H01L21/8238 ,  H01L29/786 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0948

CPC分类号： G05F1/46

摘要： A stable high-speed integrated circuit driven by a wide range of low voltages and consuming low power. A MOSFET is used wherein signals are applied to its gate and body for forming a circuit block which comprises a transistor network and at least one buffer circuit. Each buffer circuit has at least two configurations. A plurality of circuit blocks are formed on the same IC chip. Any of the configurations of the buffer circuit may be selected according to the magnitude of the capacitance of the load driven by the circuit block.

摘要翻译： 稳定的高速集成电路，由各种低电压驱动并消耗低功耗。 使用MOSFET，其中向其栅极和主体施加信号以形成包括晶体管网络和至少一个缓冲电路的电路块。 每个缓冲电路具有至少两种配置。 在同一IC芯片上形成多个电路块。 可以根据由电路块驱动的负载的电容的大小来选择缓冲电路的任何配置。

公开(公告)号：US6026480A

公开(公告)日：2000-02-15

申请号：US37067

申请日：1998-03-09

申请人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

发明人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

IPC分类号： G06F11/28 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F11/00 ,  G06F11/20 ,  G06F11/22 ,  G06F15/78 ,  G06F9/28

CPC分类号： G06F9/328 ,  G06F11/004 ,  G06F11/20 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3861

摘要： A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.

摘要翻译： 一种可重新配置电路，其中提供其指令或其解码结果和所述寄存器文件的输出的部分或全部，并且其电路结构可以通过外部信号改变。 如果当部分或全部指令或其解码结果和寄存器文件的输出满足特定条件时发生错误，则可通过外部信号重建可重构电路，以便在该特定条件下输出第一信号。 中断控制电路控制处理单元，以便基于第一信号或处理进行处理，以便在输入第一信号时避免错误。

公开(公告)号：US5895956A

公开(公告)日：1999-04-20

申请号：US569844

申请日：1995-12-08

申请人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

发明人： Yukihito Oowaki ,  Masako Yoshida ,  Makoto Yoshimi

IPC分类号： H01L21/8242 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786 ,  H01L27/01

CPC分类号： G11C11/4091 ,  H01L27/10897 ,  H01L27/12

摘要： A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

公开(公告)号：US5867040A

公开(公告)日：1999-02-02

申请号：US593275

申请日：1996-01-29

申请人： Tsuneaki Fuse ,  Yukihito Oowaki

发明人： Tsuneaki Fuse ,  Yukihito Oowaki

IPC分类号： G11C11/407 ,  G11C5/14 ,  H01L21/822 ,  H01L27/04 ,  H03K19/00 ,  H01L25/00

CPC分类号： G11C5/147 ,  H03K19/0016 ,  Y10T307/352

摘要： The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.

摘要翻译： 本发明的半导体集成电路器件包括多个集成电路。 调度电路从多个集成电路中选择任意数量的集成电路，并且将所选择的集成电路在电力线和接地线之间连接，使得所选择的集成电路串联或并联布置。 调度电路设置所选择的集成电路的连接的组合，使得所选择的集成电路的总体的消耗功率变得最小。 电压控制电路设定所选择的集成电路的串联连接部分的电位。 数据控制电路具有用于在所选择的集成电路之间输入和输出数据的输入输出电路和外部，以及用于转换某些集成电路之间的数据电平的电平转换电路。

公开(公告)号：US5463577A

公开(公告)日：1995-10-31

申请号：US365104

申请日：1994-12-28

申请人： Yukihito Oowaki ,  Takehiro Hasegawa

发明人： Yukihito Oowaki ,  Takehiro Hasegawa

IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C8/14 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404 ,  G11C11/407 ,  G11C11/24

CPC分类号： G11C8/12 ,  G11C8/14

摘要： There is provided a semiconductor memory having a reduced power consumption in data access and a high access speed in a NAND cell array scheme in which a memory cell unit is constituted by cascade-connecting a plurality of memory cells with each other. A memory cell array is divided into a plurality of sub-arrays, and the divided sub-arrays are selectively activated, thereby decreasing the capacitances of the word lines, register word lines, bit lines, and the like which are charged/discharged in data access.

摘要翻译： 提供了一种在NAND单元阵列方案中数据访问中具有降低的功耗以及高存取速度的半导体存储器，其中通过将多个存储单元彼此级联连接而构成存储单元单元。 存储单元阵列被分成多个子阵列，并且分割的子阵列被选择性地激活，从而减少在数据中被充电/放电的字线，寄存器字线，位线等的电容 访问。

公开(公告)号：US08269346B2

公开(公告)日：2012-09-18

申请号：US13047057

申请日：2011-03-14

申请人： Shoji Seta ,  Hideaki Ikuma ,  Yukihito Oowaki

发明人： Shoji Seta ,  Hideaki Ikuma ,  Yukihito Oowaki

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

摘要翻译： 半导体器件具有包括半导体衬底的LSI芯片，设置在半导体衬底的中心部分并用作半导体衬底的多层布线层的LSI芯部，与LSI的外周相邻设置的第一重新布线层 芯部，并且包括多个布线层，设置在第一重新布线层的外周的第一焊盘电极和覆盖第一焊盘电极的绝缘层。 半导体器件包括设置在LSI芯片上并包括连接到第一焊盘电极的重新布线的第二重新布线层。 半导体器件包括设置在第二重新布线层上的多个球电极。 第一再布线层与LSI芯部和第一焊盘电极电连接。