公开(公告)号：US09362159B2

公开(公告)日：2016-06-07

申请号：US14304350

申请日：2014-06-13

Applicant: Samsung Display Co., Ltd.

Inventor： Hayk Khachatryan

IPC: H01L21/762 ,  H01L21/033 ,  H01L21/70 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76254 ,  G02F1/1333 ,  H01L21/02661 ,  H01L21/0331 ,  H01L21/6835 ,  H01L21/707 ,  H01L21/76864 ,  H01L27/1266 ,  H01L2221/68318 ,  H01L2221/6835 ,  H01L2221/68381

Abstract: A method of manufacturing a display device that includes: performing a surface treatment on at least one of two opposing surfaces of a carrier substrate and a mother substrate; bonding the carrier substrate and the mother substrate; performing a thin film formation process on the mother substrate; and separating the carrier substrate and the mother substrate. The thin film formation process includes a heat treatment operation, the surface treatment includes using an inorganic acid or an organic acid, and the surface treatment controls a content of —OH, —OH2+, and —O− groups of the at least one treated surface.

Abstract translation: 一种制造显示装置的方法，包括：对载体基板和母基板的两个相对表面中的至少一个进行表面处理; 接合载体衬底和母体衬底; 在母基板上进行薄膜形成工序; 并分离载体衬底和母体衬底。 薄膜形成方法包括热处理操作，表面处理包括使用无机酸或有机酸，表面处理控制至少一个处理表面的-OH，-OH2 +和-O-基团的含量 。

公开(公告)号：US08765226B2

公开(公告)日：2014-07-01

申请号：US13419351

申请日：2012-03-13

Applicant: Scott Limb ,  Uma Srinivasan

Inventor： Scott Limb ,  Uma Srinivasan

IPC: B05D1/32 ,  C23C4/02

CPC classification number: H01L21/0331

Abstract: A patterned layer over a wafer is produced by depositing a print-patterned mask structure. Energized particles of a target material are deposited over the wafer and the print-patterned mask such that particles of said target material incident on the mask structure enter the mask structure body and minimally accumulate, if at all, on the surface of the mask structure, and otherwise the particles of target material accumulate as a generally uniform layer over the wafer. The print-patterned mask structure, including particles of target material therein, is removed leaving the generally uniform layer of target material as a patterned layer over the wafer.

Abstract translation: 通过沉积印刷图案化的掩模结构来生产晶片上的图案层。 目标材料的通电颗粒沉积在晶片和印刷图案化掩模上，使得入射到掩模结构上的所述靶材料的颗粒进入掩模结构体并且最小程度地累积在掩模结构的表面上， 否则靶材料的颗粒在晶片上聚集成大致均匀的层。 去除其中包括目标材料颗粒的印刷图案掩模结构，留下大致均匀的靶材料层作为晶片上的图案化层。

公开(公告)号：US20130040458A1

公开(公告)日：2013-02-14

申请号：US13633745

申请日：2012-10-02

Applicant: NexGen Semi Holding, Inc.

Inventor： Jeffrey Winfield Scott ,  Michael John Zani ,  Mark Joseph Bennahmias ,  Mark Anthony Mayse

IPC: H01L21/768

CPC classification number: H01J37/3174 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/3177 ,  H01L21/0331 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26533 ,  H01L21/28123 ,  H01L21/30621 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S430/143

Abstract: A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Abstract translation: 制造工艺技术使用聚焦离子束工艺在第一层上创建图案。 该图案被转移到第二层，其可以用作传统的蚀刻停止层。 图案可以形成在第二层上，而不用光线通过掩模版而没有湿化学显影，从而实现适形覆盖和非常精细的关键特征控制。 公开了两种暗场图案和光场图案，其可以实现聚焦离子束的减少或最小的曝光。

公开(公告)号：US20110236833A1

公开(公告)日：2011-09-29

申请号：US13155754

申请日：2011-06-08

Applicant: Michael CHAN

Inventor： Michael CHAN

IPC: G03F7/20

CPC classification number: H01L21/0273 ,  H01L21/0331 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/101

Abstract: A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern comprising a first grid, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, where the second photoresist pattern is a second grid which overlaps the first grid to form a photoresist web, and etching the underlying layer using the photoresist web as a mask.

Abstract translation: 制造器件的方法包括在下层上形成第一光致抗蚀剂层，图案化第一光致抗蚀剂层以形成包括第一栅格的第一光致抗蚀剂图案，使第一光致抗蚀剂图案不溶于溶剂，在第 第一光致抗蚀剂图案，图案化第二光致抗蚀剂层以在下层上形成第二光致抗蚀剂图案，其中第二光致抗蚀剂图案是与第一栅格重叠以形成光致抗蚀剂幅材的第二栅格，并且使用光致抗蚀剂幅材蚀刻下层 一个面具

公开(公告)号：US20110180850A1

公开(公告)日：2011-07-28

申请号：US12657602

申请日：2010-01-25

Applicant: Ishiang Shih ,  Chunong Qiu ,  Cindy X. Qui ,  Yi-Chi Shih

Inventor： Ishiang Shih ,  Chunong Qiu ,  Cindy X. Qui ,  Yi-Chi Shih

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L21/0331 ,  H01L29/42316

Abstract: The present invention provides methods for fabricating devices with low resistance structures involving a lift-off process. A radiation blocking layer is introduced between two resist layers in order to prevent intermixing of the photoresists. Cavities suitable for the formation of low resistance T-gates or L-gates can be obtained by a first exposure, developing, selective etching of blocking layer and a second exposure and developing. In another embodiment, a low resistance gate structure with pillars to enhance mechanical stability or strength is provided.

Abstract translation: 本发明提供了用于制造涉及剥离过程的具有低电阻结构的器件的方法。 在两个抗蚀剂层之间引入辐射阻挡层，以防止光致抗蚀剂的混合。 可以通过第一次曝光，显影，选择性蚀刻阻挡层和第二曝光和显影来获得适于形成低电阻T形栅极或L-栅极的腔体。 在另一个实施例中，提供了具有柱以提高机械稳定性或强度的低电阻门结构。

公开(公告)号：US07943521B2

公开(公告)日：2011-05-17

申请号：US12560285

申请日：2009-09-15

Applicant: Eun-Soo Jeong

Inventor： Eun-Soo Jeong

IPC: H01L21/311 ,  H01L21/461 ,  H01L21/027

CPC classification number: H01L21/32139 ,  H01L21/0331 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.

Abstract translation: 图案化半导体器件的方法可以包括在半导体衬底上形成导电层; 或者在导电层上形成正的光致抗蚀剂和负性光致抗蚀剂，通过使用正性光致抗蚀剂和负性光致抗蚀剂作为掩模选择性地去除导电层的一部分来形成多个第一导电线; 在包括第一导线和导电层的半导体衬底上形成氧化膜; 使用所述第一导线的最上表面作为目标在所述氧化物膜上进行平坦化处理; 使用氧化膜作为掩模去除多个第一导电线; 在所述半导体衬底中形成多个沟槽，并且去除所述氧化膜的一部分以暴露所述导电层的最上表面; 然后通过使用氧化膜作为掩模去除暴露的导电层来形成多个第二导电线。

公开(公告)号：US07915106B2

公开(公告)日：2011-03-29

申请号：US12270016

申请日：2008-11-13

Applicant: Jae Yeob Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

Inventor： Jae Yeob Shim ,  Hyung Sup Yoon ,  Dong Min Kang ,  Ju Yeon Hong ,  Kyung Ho Lee

IPC: H01L21/338 ,  H01L21/44 ,  H01L21/28

CPC classification number: H01L21/0331 ,  H01L21/28587

Abstract: A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

Abstract translation: 提供一种制造T型栅极的方法。 该方法包括以下步骤：在衬底上形成光致抗蚀剂层; 图案化形成在基板上的光致抗蚀剂层并形成第一开口; 在所述光致抗蚀剂层和所述基板上形成第一绝缘层; 去除所述第一绝缘层并形成第二开口以暴露所述衬底; 在所述第一绝缘层上形成第二绝缘层; 去除所述第二绝缘层并形成第三开口以暴露所述衬底; 在其上形成有光致抗蚀剂层和第三开口的第二绝缘层上形成金属层; 并除去形成在光致抗蚀剂层上的金属层。 因此，可以通过沉积绝缘层和橡皮干蚀刻工艺来形成限定栅极长度的均匀且精细的开口，因此可以制造更精细的微型T型栅电极。

公开(公告)号：US20110024799A1

公开(公告)日：2011-02-03

申请号：US12845292

申请日：2010-07-28

Applicant: Yuichi Minoura ,  Toshihide Kikkawa

Inventor： Yuichi Minoura ,  Toshihide Kikkawa

IPC: H01L29/205 ,  H01L21/20 ,  H01L21/335 ,  H01L33/00

CPC classification number: H01L21/30617 ,  B82Y20/00 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/0331 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01S5/0201 ,  H01S5/0216 ,  H01S5/0217 ,  H01S5/02476 ,  H01S5/34333

Abstract: A method for manufacturing a compound semiconductor device includes forming a first compound semiconductor layer over a first substrate, the first compound semiconductor layer containing AlxGa1-xN (0≦x

Abstract translation: 一种化合物半导体器件的制造方法，包括在第一衬底上形成第一化合物半导体层，所述第一化合物半导体层含有具有第一带隙的Al x Ga 1-x N（0＆lt; n 1; x 1） 在所述第一化合物半导体层上形成第二化合物半导体层，所述第二化合物半导体层包含具有大于所述第一带隙的第二带隙的Al y In z Ga 1-y-z N（0

公开(公告)号：US07677696B2

公开(公告)日：2010-03-16

申请号：US11084042

申请日：2005-03-21

Applicant: Koji Kitani

Inventor： Koji Kitani

IPC: B41J2/01

CPC classification number: H01L21/6715 ,  B41J2/14129 ,  B41J2/1603 ,  B41J2/1607 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1646 ,  H01L21/0331 ,  H01L21/76838

Abstract: In order to suppress peeling of a film formed on a base, and improve the durability and reliability of the film, an overhang is provided on a side surface of a sacrifice layer, whereby a film is formed, which has an edge portion having a thickness distribution, in which a thickness is gradually decreased to substantially zero at an edge of a formed film.

Abstract translation: 为了抑制在基材上形成的膜的剥离，提高膜的耐久性和可靠性，在牺牲层的侧面设置有突出部，由此形成膜，其具有厚度 分布，其中在成形膜的边缘处的厚度逐渐减小到基本上为零。

公开(公告)号：US07651936B2

公开(公告)日：2010-01-26

申请号：US11945091

申请日：2007-11-26

Applicant: Eun-Soo Jeong

Inventor： Eun-Soo Jeong

IPC: H01L21/44

CPC classification number: H01L21/32139 ,  H01L21/0331 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer; forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.

Abstract translation: 图案化半导体器件的方法可以包括在半导体衬底上形成导电层; 或者在导电层上形成正的光致抗蚀剂和负性光致抗蚀剂; 通过使用正性光致抗蚀剂和负性光致抗蚀剂作为掩模选择性地去除导电层的一部分来形成多个第一导电线; 在包括第一导线和导电层的半导体衬底上形成氧化膜; 使用所述第一导线的最上表面作为目标在所述氧化物膜上进行平坦化处理; 使用氧化膜作为掩模去除多个第一导电线; 在所述半导体衬底中形成多个沟槽，并且去除所述氧化膜的一部分以暴露所述导电层的最上表面; 然后通过使用氧化膜作为掩模去除暴露的导电层来形成多个第二导电线。