公开(公告)号：US20030093750A1

公开(公告)日：2003-05-15

申请号：US10325525

申请日：2002-12-19

申请人： Broadcom Corporation pursuant

发明人： Kelly Cameron

IPC分类号： H03M013/00

CPC分类号： H03M13/2782 ,  H03M13/00 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2789

摘要： A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

摘要翻译： 具有存储器阵列的存储器高效卷积交织器/解交织器，写入换向器和读取换向器，其中换向器在预定延迟之后相对于预先选择的存储器单元执行它们各自的写入和读取操作。 使用基于模的技术来选择延迟，使得实现了Ramsey II型交织器的有效实现。

公开(公告)号：US06546520B1

公开(公告)日：2003-04-08

申请号：US09430456

申请日：1999-10-29

申请人： Kelly Cameron

发明人： Kelly Cameron

IPC分类号： H03M1303

CPC分类号： H03M13/2782 ,  H03M13/00 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2789

摘要： A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation: of a Ramsey Type-II interleaver is realized.

摘要翻译： 具有存储器阵列的存储器高效卷积交织器/解交织器，写入换向器和读取换向器，其中换向器在预定延迟之后相对于预先选择的存储器单元执行它们各自的写入和读取操作。 使用基于模的技术来选择延迟，使得实现了Ramsey Type-II交织器的有效实现。

公开(公告)号：US20020053050A1

公开(公告)日：2002-05-02

申请号：US09988979

申请日：2001-11-19

申请人： SONY CORPORATION

发明人： Susumu Senshu

IPC分类号： G06F011/00

CPC分类号： H03M13/276 ,  G11B7/007 ,  G11B20/1866 ,  H03M13/27

摘要： An optical disc recording/reproducing method, an optical disc and an optical disc device in which a logical format which has enabled long interleaving is constituted by a large block to enable data recording/reproduction to high reliability. Data is recorded/reproduced in accordance with a disc format in which an ECC block formed by a first error correction code C1 interleaved with respect to the direction of data on the disc and a second code C2 having the direction of the data different from that of the first error correction code is made up of one or more sectors and in which an information word portion of the first error correction code in the ECC block is made up of the interleaved second code.

摘要翻译： 一种光盘记录/再现方法，光盘和光盘装置，其中使得能够进行长交织的逻辑格式由大块构成，以使数据记录/再现成为高可靠性。 根据盘格式对数据进行记录/再现，其中由相对于盘上数据方向交错的第一纠错码C1形成的ECC块和数据方向不同于第 第一纠错码由一个或多个扇区组成，其中ECC块中的第一纠错码的信息字部分由交错的第二码组成。

公开(公告)号：US20020029364A1

公开(公告)日：2002-03-07

申请号：US09742248

申请日：2000-12-20

发明人： Brian S. Edmonston ,  Paul K. Gray

IPC分类号： G06F011/00 ,  H03M013/00

CPC分类号： H03M13/3905 ,  H03M13/27 ,  H03M13/276 ,  H03M13/2767 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/6362 ,  H03M13/6561 ,  H03M13/6566 ,  H04L1/0055 ,  H04L1/0068 ,  H04L1/0071 ,  H05K1/0393 ,  H05K1/095 ,  H05K3/1275 ,  H05K2203/0113 ,  H05K2203/0278 ,  H05K2203/0534

摘要： A system and method for high efficiency high performance processing of turbo codes is described. In accordance with one embodiment of the invention, an interleaver for interleaving code symbols is providing, the interleaver having a plurality of subsections, each subsection having a set of addresses and each address having an index, wherein a substantially constant relationship exists from any one subsection to any other subsection between the index of each address at a particular location.

摘要翻译： 描述了用于turbo码的高效率高性能处理的系统和方法。 根据本发明的一个实施例，用于交织代码符号的交织器提供具有多个子部分的交织器，每个子部分具有一组地址，每个地址具有索引，其中从任何一个子部分存在基本恒定的关系 到特定位置的每个地址的索引之间的任何其他小节。

公开(公告)号：US06334197B1

公开(公告)日：2001-12-25

申请号：US09375067

申请日：1999-08-16

申请人： Mustafa Eroz ,  A. Roger Hammons, Jr. ,  Feng-Wen Sun

发明人： Mustafa Eroz ,  A. Roger Hammons, Jr. ,  Feng-Wen Sun

IPC分类号： H03M1327

CPC分类号： H03M13/271 ,  H03M13/2735 ,  H03M13/2746 ,  H03M13/276 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2789 ,  H03M13/2957

摘要： A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

摘要翻译： 公开了一种交织具有不同长度的索引数据块的方法。 该方法包括以下步骤：提供一组基本交错器，其包括索引数据的一个或多个排列的族，并具有可变长度; 基于所需的交织器长度L选择基本交织器之一; 并且使所选择的基本交织器适配以产生具有期望的交织器长度L的交织器。

公开(公告)号：US06289486B1

公开(公告)日：2001-09-11

申请号：US09126250

申请日：1998-07-30

申请人： Pil Joong Lee ,  Young Kim ,  Chang Soo Park ,  Hyeon Woo Lee ,  Jun Jin Kong

发明人： Pil Joong Lee ,  Young Kim ,  Chang Soo Park ,  Hyeon Woo Lee ,  Jun Jin Kong

IPC分类号： H03M1300

CPC分类号： H04L1/0065 ,  H03M13/2721 ,  H03M13/276 ,  H03M13/2767 ,  H03M13/2957 ,  H03M13/2972 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0071

摘要： There is provided a channel encoder having convolutional encoders concatenated in parallel or in series. The channel encoder includes a first encoder for encoding input information bits, an interleaver having a memory and an index generator, for modifying the order of the information bits in a predetermined method, a second encoder for encoding the output of the interleaver, first and second terminating devices for terminating frames of input and output information bits of the first and second encoders, a tail bit generator for storing tails bits used in frame termination, and a controller and a switch for controlling the above procedure.

摘要翻译： 提供了并行或串联连接的卷积编码器的信道编码器。 信道编码器包括用于编码输入信息比特的第一编码器，具有存储器和索引生成器的交织器，用于以预定方法修改信息比特的顺序，用于对交织器的输出进行编码的第二编码器，第一和第二 用于终止第一和第二编码器的输入和输出信息比特帧的终端装置，用于存储在帧终止中使用的尾部比特的尾比特发生器，以及用于控制上述过程的控制器和开关。

公开(公告)号：US5537420A

公开(公告)日：1996-07-16

申请号：US238259

申请日：1994-05-04

申请人： Zheng Huang

发明人： Zheng Huang

IPC分类号： G06F11/10 ,  H03M13/27 ,  H04L27/00 ,  G06F11/00

CPC分类号： H03M13/2782 ,  H03M13/2732 ,  H03M13/276

摘要： A convolutional interleaver and addressing scheme where up to B consecutive symbols containing errors can be interleaved such that they are separated from each other by at least N intervening symbols. Memory, such as RAM, is configured with (B-1) cells of increasing size for storing symbols from a data stream. A first one of the cells has M storage locations which store M symbols. Each successive one of the cells has M more storage locations than the immediately preceding cell for storing M more symbols than the immediately preceding cell, where M=N/B. The cells are successively addressed to write a next symbol from the stream into a next write symbol location in a currently addressed cell and to read a symbol from the location of the currently addressed cell immediately following the next write symbol location. The locations are accessed in a first revolving manner such that the last location in a cell is followed by the first location in that cell. The cells are addressed in a second revolving manner such that the (B-1)th cell is followed by the first cell, or vice versa. An intervening transfer stage between the (B-1)the cell and the first cell to directly transfers the next symbol to the interleaver output. Each consecutive symbol from the stream is written into a next consecutive one of the cells. A deinterleaver has the same structure.

摘要翻译： 卷积交织器和寻址方案，其中可以交织包含错误的B个连续符号，使得它们彼此间隔至少N个中间符号。 诸如RAM的存储器被配置为具有增加大小的（B-1）个单元，用于存储来自数据流的符号。 第一个单元具有存储M个符号的M个存储位置。 每个连续的一个单元具有比紧前面的单元更多的存储位置，用于存储比前一个单元更多的符号，其中M = N / B。 连续寻址小区以将下一个符号从流写入当前寻址的小区中的下一个写符号位置，并从紧跟在下一个写符号位置之后的当前寻址的单元的位置读取符号。 以第一旋转方式访问位置，使得单元中的最后位置后跟该单元中的第一位置。 以第二循环方式寻址小区，使得（B-1）小区后面是第一个小区，反之亦然。 （B-1）小区和第一小区之间的中间传送级，以将下一个符号直接传送到交织器输出。 来自流的每个连续符号被写入下一个连续的一个单元。 解交织器具有相同的结构。

公开(公告)号：US20230384931A1

公开(公告)日：2023-11-30

申请号：US18229814

申请日：2023-08-03

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Kai CHIRCA ,  Matthew David PIERSON

IPC分类号： G06F3/06 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC分类号： G06F3/0604 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/1668 ,  G06F13/4027 ,  G06F12/0855 ,  G06F12/0607 ,  G06F12/0828 ,  G06F12/0831 ,  G06F13/124 ,  G06F3/0607 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0815 ,  G06F12/0857 ,  G06F13/1663 ,  G06F3/0632 ,  G06F3/0673 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F9/30101 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F13/1642 ,  G06F3/064 ,  G06F9/30123 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/657 ,  G06F2212/304 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1016 ,  G06F12/0846

摘要： A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

公开(公告)号：US09252834B2

公开(公告)日：2016-02-02

申请号：US14170170

申请日：2014-01-31

申请人： Olivier B. A. Seller ,  Nicolas Sornin

发明人： Olivier B. A. Seller ,  Nicolas Sornin

IPC分类号： H04B1/66 ,  H03M13/27 ,  H04B1/69 ,  H03M5/14

CPC分类号： H04B1/66 ,  H03M5/14 ,  H03M13/2721 ,  H03M13/276 ,  H04B1/69 ,  H04B2001/6912

摘要： A transmitter device arranged to encode a set of digital input data into a succession of modulated chirps, whereby said digital input data are encoded according to a Gray code into codewords (320, 321, 322) having a plurality of bits, and having an interleaver that distributes the bits (C00, . . . Cnn) of each codeword into a series of digital modulation values (S0, . . . S7), at different bit positions, and to synthesize a series of modulated chirps whose cyclical shifts are determined by the modulation values. A special frame structure is defined in order to ensure high robustness, and variable bit-rate flexibility.

摘要翻译： 一种发射机设备，被配置为将一组数字输入数据编码成一系列调制啁啾，由此所述数字输入数据根据格雷码被编码成具有多个比特的码字（320,321,322），并具有交织器 将每个码字的比特（C00，...，Cnn）分配到一系列数字调制值（S0，...，S7）中，并在不同的比特位置合成一系列调制的线性调频脉冲，其循环移位由 调制值。 定义了一个特殊的框架结构，以确保高稳健性和可变位速率的灵活性。

公开(公告)号：US20150263765A1

公开(公告)日：2015-09-17

申请号：US14596709

申请日：2015-01-14

申请人： HI-TREND TECHNOLOGY (SHANGHAI) CO., LTD.

发明人： Xuming ZHANG

IPC分类号： H03M13/27 ,  H03M13/17

CPC分类号： H03M13/276 ,  H03M13/275

摘要： The present invention relates to communication field, disclosing a data block interleaving and deinterleaving method and apparatus for communication equipments. In the present invention, a recursive method for calculating interleaver or deinterleaver addresses for existing power line communication standards is proposed. The complex modulo operation is simplified to a series of Add-Compare-Subtract operations. Therefore, the hardware implementation complexity is significantly reduced.

摘要翻译： 本发明涉及通信领域，公开了通信设备的数据块交织和解交织方法及装置。 在本发明中，提出了用于计算现有电力线通信标准的交织器或解交织器地址的递归方法。 复数模运算被简化为一系列加法比较减法运算。 因此，硬件实现复杂度大大降低。