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公开(公告)号：US09735353B2
公开(公告)日：2017-08-15
申请号：US15098025
申请日：2016-04-13
Inventor： Philippe Boivin , Simon Jeannot
CPC classification number: H01L45/06 , G11C13/0004 , G11C2213/79 , G11C2213/82 , H01L27/2436 , H01L27/2463 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666
Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
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公开(公告)号：US20170227602A1
公开(公告)日：2017-08-10
申请号：US15244586
申请日：2016-08-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sylvain Clerc , Gilles Gasiot
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31703 , G01R31/31723 , G01R31/31727 , G01R31/318392 , G01R31/318566
Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.
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公开(公告)号：US20170199329A1
公开(公告)日：2017-07-13
申请号：US15217100
申请日：2016-07-22
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Jean-Francois CARPENTIER , Patrick LEMAITRE , Mickael FOUREL
CPC classification number: G02B6/12002 , G02B6/12004 , G02B6/30 , G02B6/4232 , G02B6/4257 , G02B6/4269 , G02B6/428 , G02B6/4292 , H01L23/13 , H01L23/49827 , H01L2224/16225
Abstract: An integrated electronic device includes a substrate having an opening extending therethrough. The substrate includes an interconnection network, and connections coupled to the interconnection network. The connections are to be fixed on a printed circuit board. An integrated photonic module is electrically connected to the substrate, with a portion of the integrated photonic module in front of or overlapping the opening of the substrate. An integrated electronic module is electrically connected to the photonic module, and extends at least partly into the opening of the substrate. The electronic module and the substrate may be electrically connected onto the same face of the photonic module.
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公开(公告)号：US09704709B2
公开(公告)日：2017-07-11
申请号：US15260767
申请日：2016-09-09
Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives , STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Augendre , Aomar Halimaoui , Sylvain Maitrejean , Shay Reboh
IPC: H01L21/02 , H01L21/265 , H01L21/266 , H01L29/10 , H01L21/8234 , H01L21/84 , H01L29/165 , H01L29/66
CPC classification number: H01L21/02694 , H01L21/0245 , H01L21/02532 , H01L21/02592 , H01L21/02667 , H01L21/26586 , H01L21/266 , H01L21/823412 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/66568 , H01L29/66742 , H01L29/66772 , H01L29/7847 , H01L29/78654 , H01L29/78681 , H01L29/78687
Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).
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公开(公告)号：US20170194368A1
公开(公告)日：2017-07-06
申请号：US15392032
申请日：2016-12-28
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Francois Roy , Boris Rodrigues , Marie Guillon , Yvon Cazaux , Benoit Giffard
IPC: H01L27/146 , H04N5/374
CPC classification number: G01S7/4863 , G01S7/4914 , H01L27/14607 , H01L27/1461 , H01L27/14612 , H01L27/14625 , H01L27/1463 , H01L27/14641 , H01L27/14643 , H01L27/14645 , H01L27/14683 , H04N5/374
Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.
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Patent Agency Ranking
公开(公告)号：US20170192090A1
公开(公告)日：2017-07-06
申请号：US15387883
申请日：2016-12-22
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Francois Roy , Marie Guillon , Yvon Cazaux , Boris Rodrigues , Alexis Rochas
IPC: G01S7/486 , H01L27/146
CPC classification number: G01S7/4863 , G01S7/4914 , H01L27/14607 , H01L27/1461 , H01L27/14612 , H01L27/14625 , H01L27/1463 , H01L27/14641 , H01L27/14643 , H01L27/14645 , H01L27/14683 , H04N5/374
Abstract: A time-of-flight detection pixel includes a photosensitive area including a first doped layer and a charge collection area extending in the first doped layer. At least two charge storage areas extend from the charge collection area, each including a first well more heavily doped than the charge collection area and separated from the charge collection area by a first portion of the first doped layer which is coated with a gate. Each charge storage area is laterally delimited by two insulated conductive electrodes, extending parallel to each other and facing each other. A second heavily doped layer of opposite conductivity coats the pixel except for at each portion of the first doped layer coated with the gate.
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公开(公告)号：US20170179196A1
公开(公告)日：2017-06-22
申请号：US15387850
申请日：2016-12-22
Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives , STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA
Inventor： Laurent GRENOUILLET , Sotirios Athanasiou , Philippe Galy
CPC classification number: H01L27/2454 , G11C13/0007 , G11C13/0069 , G11C2213/53 , H01L27/101 , H01L27/1207 , H01L27/2436 , H01L28/00 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/147
Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.
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公开(公告)号：US20170179104A1
公开(公告)日：2017-06-22
申请号：US15137201
申请日：2016-04-25
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Alexandre Ayres , Bertrand Borot
IPC: H01L27/02 , H01L23/532 , H01L27/088 , H01L23/522 , H01L23/528
CPC classification number: H01L27/0207 , G06F17/5068 , G06F17/5077 , H01L23/5226 , H01L23/528 , H01L23/53228 , H01L27/088
Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.
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公开(公告)号：US20170162672A1
公开(公告)日：2017-06-08
申请号：US15372930
申请日：2016-12-08
Applicant: Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Louis HUTIN , Julien BORREL , Yves MORAND , Fabrice NEMOUCHI
CPC classification number: H01L29/66643 , H01L29/0895 , H01L29/66636 , H01L29/7839
Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.
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公开(公告)号：US09653538B2
公开(公告)日：2017-05-16
申请号：US14220542
申请日：2014-03-20
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Frederic Boeuf , Olivier Weber
IPC: H01L21/00 , H01L21/762 , H01L21/02 , H01L29/78 , H01L21/84 , H01L21/324 , H01L29/06 , H01L27/12
CPC classification number: H01L29/7847 , H01L21/02381 , H01L21/02422 , H01L21/02532 , H01L21/02639 , H01L21/02667 , H01L21/76264 , H01L21/76283 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/12 , H01L27/1203 , H01L29/0611 , H01L29/0642 , H01L29/16 , H01L29/161 , H01L29/7838
Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.
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