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公开(公告)号：US20190001463A1
公开(公告)日：2019-01-03
申请号：US16123383
申请日：2018-09-06
发明人： Hiromasa HASHIMOTO , Masanao SASAKI
摘要： A workpiece polishing apparatus including a polishing pad to polish a workpiece, a polishing agent supplying mechanism to supply a polishing agent, and a polishing head to hold the workpiece such that a back surface of the workpiece is held by a backing pad and an edge of the workpiece is held by an annular template. This apparatus polishes the workpiece by pressing the workpiece and the template against the polishing pad and thereby bringing the workpiece into sliding contact with the polishing pad. The template is made of a resin containing filler or woven fabric and has fine depressions created by filler or woven fabric exposed on the surface on the side that presses the polishing pad. This apparatus can stabilize the polishing rate of the outer circumferential portion of the workpiece and thereby polish the workpiece into a very flat workpiece.
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公开(公告)号：US10166649B2
公开(公告)日：2019-01-01
申请号：US15523817
申请日：2015-10-21
发明人： Taichi Yasuda , Tatsuo Enomoto
IPC分类号： B24B37/08 , B24B37/005 , B24B37/34 , B24B49/10
摘要： A machining apparatus for a workpieces includes an upper turn table support mechanism supporting an upper turn table from above to be vertically movable by a cylinder extending along a rotational axis direction of the table, a horizontal plate fixed to the cylinder so that a main surface thereof becomes perpendicular to a longitudinal axis of the cylinder, at least three displacement sensors which measure horizontal plate surface height positions when the upper turn table has moved down to a fixed position, and a control apparatus to calculate a relative upper turn table height position and an angle formed between the upper turn table rotational axis and the cylinder longitudinal axis from the horizontal plate surface height positions measured by the displacement sensors. A workpiece holding abnormality can be accurately and quickly detected before machining the workpiece to avoid damage, and an cylinder eccentric angle can be detected during machining.
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公开(公告)号：US20180369984A1
公开(公告)日：2018-12-27
申请号：US15777745
申请日：2016-11-29
发明人： Masaaki OSEKI , Michito SATO , Kaoru ISHII
IPC分类号： B24B37/015 , H01L21/306 , H01L21/66
摘要： A polishing method including polishing to polish a surface of a wafer by sliding the wafer held by a polishing head on a surface of a polishing pad while supplying a polishing slurry to the polishing pad attached to a turntable, the method including correlation derivation to obtain a correlation between a surface temperature of the polishing pad and a haze level of a wafer polished with the use of the polishing pad in advance before performing the polishing, and also the wafer is polished in the polishing while controlling the surface temperature of the polishing pad based on the correlation between the surface temperature of the polishing pad and the haze level of the wafer polished with the use of the polishing pad. Consequently, the polishing method can control a haze in polishing a wafer and thereby prolong the service life of the polishing pad.
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公开(公告)号：US10147656B2
公开(公告)日：2018-12-04
申请号：US15576120
申请日：2016-03-17
发明人： Shigeru Oba , Shiro Amagai
IPC分类号： H01L21/66 , B24B37/013 , B24B37/07 , B24B49/12 , H01L21/306 , B24B37/08 , B24B37/20 , H01L21/02
摘要： A sizing device in a polishing apparatus for measuring a thickness of a wafer in course of polishing by laser beam interference, includes: a light-source for irradiating the wafer in course of polishing with a laser beam, a light-receiving portion for receiving reflected light from the wafer in course of polishing irradiated with the laser beam from the light-source, a calculating part for calculating a measured value of the thickness of the wafer in course of polishing irradiated with the laser beam based on the reflected light received through the light-receiving portion. The calculating part can calculate the wafer thickness in course of polishing by calculating a measuring error value of the wafer thickness in course of polishing from resistivity of the wafer in course of polishing based on a previously determined correlation between wafer resistivity and measuring error value of wafer thickness, and by compensating the measuring error value.
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公开(公告)号：US10119193B2
公开(公告)日：2018-11-06
申请号：US15534904
申请日：2015-11-17
发明人： Hideki Hariya
IPC分类号： C30B25/12 , C23C16/52 , C30B29/06 , C30B25/18 , C30B25/20 , C30B33/02 , H01L21/02 , H01L21/205 , H01L21/322 , C23C16/46
摘要： Provided is a method of manufacturing an epitaxial wafer, which includes vapor-phase growing an epitaxial layer on a substrate W placed on a susceptor 3 in a state where an upper surface 4b1 of a lift pin 4 inserted in a through-hole H of the susceptor 3 retracts or projects with respect to an upper opening H1a of the through-hole H. A level difference D from the upper surface 4b1 of the lift pin 4 to the opening H1a of the through-hole H is measured with laser light, and outputs, during epitaxial growth, of heaters 9 located above and beneath the susceptor 3 are adjusted on the basis of the measured level difference D. Thus, a method of manufacturing an epitaxial wafer, which facilitates adjustment of the outputs of the heat sources during epitaxial growth, is provided.
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公开(公告)号：US10100430B2
公开(公告)日：2018-10-16
申请号：US14420806
申请日：2013-08-05
发明人： Ryoji Hoshi , Masanori Takazawa
摘要： A method for growing a silicon single crystal by a Czochralski method, includes: conducting preliminary examination of growth conditions under which crystal collapse does not occur, the preliminary examination being based on a correlation between presence or absence of the crystal collapse in the silicon single crystal and a position at which an internal stress in the crystal when the silicon single crystal is grown will exceed a prescribed threshold, the position being away from a crystal growth interface; and growing the silicon single crystal in accordance with the growth conditions under which the crystal collapse does not occur, the growth conditions being determined from the preliminary examination. The method can grow a silicon single crystal while crystal collapse is effectively prevented.
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公开(公告)号：US20180290261A1
公开(公告)日：2018-10-11
申请号：US15768970
申请日：2016-10-17
发明人： Kazuya SATO , Hiromasa HASHIMOTO , Naoki KAMIHAMA
IPC分类号： B24B37/013 , B24B37/04 , B24B37/20 , B24B49/12 , H01L21/66 , H01L21/306
摘要： The present invention provides a method for polishing a wafer including, after unloading and before loading to hold, a next wafer to be polished: measurement to measure a depth PDt of a concave portion of a template after taking out a polished wafer; calculation to calculate a difference ΔPD between the measured depth PDt of the concave portion and a depth PD0 of the concave portion of the template before being used for polishing; and adjustment to adjust polishing conditions for a next wafer to be polished in accordance with the calculated difference ΔPD. Consequently, there are provided the method for polishing a wafer and a polishing apparatus which enable adjusting a fluctuation in flatness of each wafer caused due to a fluctuation in numerical value of a pocket depth of a template.
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公开(公告)号：US10066322B2
公开(公告)日：2018-09-04
申请号：US15680949
申请日：2017-08-18
发明人： Ryoji Hoshi , Hiroyuki Kamada
摘要： A method for a heat treatment of a silicon single crystal wafer in an oxidizing ambient, including: performing the heat treatment based on a condition determined by a tripartite correlation between a heat treatment temperature during the heat treatment, an oxygen concentration in the silicon single crystal wafer before the heat treatment, and a growth condition of a silicon single crystal from which the silicon single crystal wafer is cut out. This provides a method for a heat treatment of a silicon single crystal wafer which can annihilate void defects or micro oxide precipitate nuclei in a silicon single crystal wafer with low cost, efficiently, and securely by a heat treatment in an oxidizing ambient.
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公开(公告)号：US20180247830A1
公开(公告)日：2018-08-30
申请号：US15544359
申请日：2016-01-07
发明人： Katsuyoshi SUZUKI , Hiroshi TAKENO , Koji EBARA
IPC分类号： H01L21/322 , C30B15/00 , C30B29/06 , C30B33/02
CPC分类号： H01L21/3225 , C30B15/00 , C30B29/06 , C30B33/02 , C30B33/12 , H01L21/26 , H01L21/322
摘要： A method for manufacturing a silicon wafer having a denuded zone in a surface layer by performing a heat treatment to a silicon wafer, including: a step A, performing a first rapid heat treatment of 0.01 msec or more and 100 msec or less to an upper surface layer alone of the silicon wafer to be treated at 1300° C. or more and a silicon melting point or less by using a first heat source which heats the silicon wafer to be treated from above; and a step B, holding the silicon wafer to be treated at 1100° C. or more and less than 1300° C. for one second or more and 100 seconds or less by a second rapid heat treatment using a second heat source which heats the silicon wafer to be heated, and decreasing the temperature at a falling rate of 30° C./sec or more and 150° C./sec or less.
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公开(公告)号：US20180245240A1
公开(公告)日：2018-08-30
申请号：US15902418
申请日：2018-02-22
发明人： Kazunori HAGIMOTO , Masaru SHINOMIYA , Keitaro TSUCHIYA , Hirokazu GOTO , Ken SATO , Hiroshi SHIKAUCHI , Shoichi KOBAYASHI , Hirotaka KURIMOTO
IPC分类号： C30B33/00 , H01L21/02 , C30B25/00 , H01L21/66 , H01L29/32 , C30B33/10 , C30B29/40 , C30B25/18 , C23C16/56 , C23C16/34 , H01L29/20 , H01L21/78
CPC分类号： C30B33/00 , C23C16/34 , C23C16/56 , C30B25/00 , C30B25/183 , C30B29/406 , C30B33/10 , H01L21/02013 , H01L21/02019 , H01L21/02021 , H01L21/02024 , H01L21/02378 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/7806 , H01L22/12 , H01L22/20 , H01L29/2003 , H01L29/32
摘要： A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided.
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