公开(公告)号：US07483244B2

公开(公告)日：2009-01-27

申请号：US11213525

申请日：2005-08-26

申请人： Takanori Sato

发明人： Takanori Sato

IPC分类号： G11B5/39

CPC分类号： G11B5/584

摘要： In a helical scanning tape system including a magnetoresistive head; and a magnetic recording medium having a magnetic layer formed by oblique evaporation on a long nonmagnetic support, a signal being read with the magnetoresistive head by helical scanning, the track width of the magnetoresistive head is 0.5 to 0.8 μm, the distance between shields is 0.13 to 0.145 μm, and sensitivity is 1,862 μVp-p or more.

摘要翻译： 在包括磁阻头的螺旋扫描带系统中; 磁记录介质具有通过在非磁性载体上长时间倾斜蒸发形成的磁性层，通过螺旋扫描用磁阻磁头读取信号，磁阻磁头的磁道宽度为0.5至0.8μm，屏蔽之间的距离为0.13 至0.145μm，灵敏度为1862μVp-p以上。

公开(公告)号：US07469367B2

公开(公告)日：2008-12-23

申请号：US11633547

申请日：2006-12-04

申请人： Shinobu Nakamura ,  Mamoru Kudo ,  Satoru Ooshima ,  Jun Yamane ,  Hirofumi Shimizu

发明人： Shinobu Nakamura ,  Mamoru Kudo ,  Satoru Ooshima ,  Jun Yamane ,  Hirofumi Shimizu

IPC分类号： H03M13/00

CPC分类号： G11B20/1025 ,  G11B19/04 ,  G11B20/10212 ,  G11B20/10333 ,  G11B20/10425 ,  G11B20/1403 ,  G11B27/3027 ,  G11B2220/2562 ,  H03L7/107 ,  H03L2207/06 ,  H04N5/935

摘要： In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel clock so as to extract data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

摘要翻译： 在数字PLL系统中，代替使用高频时钟测量二值化的重放RF信号，通过使用N个相位时钟（例如，16个相位时钟）产生脉冲长度数据。 然后用虚拟通道时钟对脉冲长度数据进行游程长度计数，以便提取数据。 在该数字PLL系统中，检测在N相时钟的相邻时钟之间的间隔期间的异步信号的变化点数，以便根据检测到的变化点数确定相位误差。 也可以根据与N相时钟同步的信号的变化点与N相时钟的每个时钟之间的时序关系来确定相位误差。

公开(公告)号：US07457079B2

公开(公告)日：2008-11-25

申请号：US10606108

申请日：2003-06-25

申请人： Kazushi Ogawa ,  Teiichi Miyauchi ,  Tadashi Ozue

发明人： Kazushi Ogawa ,  Teiichi Miyauchi ,  Tadashi Ozue

IPC分类号： G11B5/17 ,  G11B5/255 ,  G11B5/31 ,  G11B5/53 ,  G11B5/265 ,  G11B5/39

CPC分类号： G11B5/3967 ,  G11B5/23 ,  G11B5/2452 ,  G11B5/3106 ,  G11B5/3109 ,  G11B5/3116 ,  G11B5/312 ,  G11B5/313 ,  G11B5/3146 ,  G11B5/3156 ,  G11B5/3903 ,  G11B5/4886 ,  G11B5/4893 ,  G11B5/53

摘要： A thin film magnetic recording head comprises a substrate, a first magnetic core formed on the substrate, a second magnetic core having the front end face with a magnetic gap with respect to the front end face of the first magnetic core, and a coil for developing magnetic flux between the front end portions of the magnetic cores. A width of the second magnetic core at the front end portion thereof is chosen to be smaller than that of the first magnetic core. The second magnetic core is at a leading position relative to the second magnetic core in a traveling direction on a recording medium. In such configuration, it is possible to reduce side erase due to recording magnetic flux fringing and to achieve high density of magnetic recording while maintaining the conventional fabrication steps for the thin film magnetic recording head, thereby avoiding the problem in the fabrication.

摘要翻译： 薄膜磁记录头包括基板，形成在基板上的第一磁芯，具有相对于第一磁芯的前端面具有磁隙的前端面的第二磁芯和用于显影的线圈 磁芯的前端部之间的磁通量。 第二磁芯在其前端部分的宽度被选择为小于第一磁芯的宽度。 第二磁芯相对于第二磁芯在记录介质上的行进方向上处于前导位置。 在这种结构中，由于记录磁通边缘而可能减少侧面擦除并且在保持薄膜磁记录头的常规制造步骤的同时实现高密度的磁记录，从而避免了制造中的问题。

公开(公告)号：US07423570B2

公开(公告)日：2008-09-09

申请号：US11506989

申请日：2006-08-18

申请人： Go Asayama ,  Noriyuki Fukushima ,  Yoshikazu Nitta ,  Yoshinori Muramatsu ,  Kiyotaka Amano

发明人： Go Asayama ,  Noriyuki Fukushima ,  Yoshikazu Nitta ,  Yoshinori Muramatsu ,  Kiyotaka Amano

IPC分类号： H03M1/66

CPC分类号： H03M1/1014 ,  H03M1/66 ,  H03M1/742 ,  H04N5/378

摘要： A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.

摘要翻译： DA转换器包括用于根据数字输入信号值获得模拟输出信号的第一DA转换部分和用于根据数字增益控制输入信号值获得模拟增益控制输出信号的第二DA转换部分。 在DA转换器中，由第一DA转换部生成的模拟输出信号的增益控制基于由第二DA转换部生成的增益控制输出信号进行。

公开(公告)号：US07420127B2

公开(公告)日：2008-09-02

申请号：US11644143

申请日：2006-12-22

申请人： Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

发明人： Hiroshi Asami ,  Hidetoshi Kusano ,  Yuji Nishitani ,  Ken Orui

IPC分类号： H05K1/02

CPC分类号： H05K3/4694 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4617 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/09536 ,  H05K2201/09881 ,  H05K2201/09972 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.

摘要翻译： 本发明提供一种制造多层布线基板的方法，其可以以细间距保持导体图案的尺寸稳定性，从材料选择的角度解决对工艺的限制，并且进一步降低制造成本，并且 多层布线基板。 形成在由金属制成的支撑片和粘合剂层上的第二布线基板通过使用支撑片部分堆叠在第一布线基板的预定区域上。 在第二布线基板的层叠之后，最后蚀刻并去除支撑片。 第二布线基板仅堆叠在第一布线基板上需要多层的部分上，从而减少第二布线基板的结构材料的量。

公开(公告)号：US07419512B2

公开(公告)日：2008-09-02

申请号：US11599230

申请日：2006-11-13

申请人： Yoshinari Sasaki ,  Koji Shimotoku ,  Hidehisa Murase

发明人： Yoshinari Sasaki ,  Koji Shimotoku ,  Hidehisa Murase

IPC分类号： H01M4/04 ,  H01M4/70

CPC分类号： H01M4/13 ,  H01M2/26 ,  H01M4/04 ,  H01M4/0404 ,  H01M4/70 ,  H01M10/0436 ,  H01M10/0525 ,  Y10T29/49108 ,  Y10T29/49115

摘要： An electrode includes a composite mixture layer formed by applying a composite mixture having one of a cathode active material or an anode active material on one of main surfaces of a plurality of current collectors formed in substantially rectangular shapes; and a non-applied part to which the composite mixture is not applied at both end parts in the longitudinal direction. One current collector is connected to the other adjacent current collector at one end side in the longitudinal direction through a connecting part to which the composite mixture is not applied and which is provided continuously to the non-applied parts. In the electrode constructed as described above, a plurality of current collectors can be laminated to obtain a multi-layer structure and an electric current can be collected from a lead welded to only one end part of the current collector. Thus, the electrode of a new form having an excellent productivity and a high capacity can be provided.

摘要翻译： 电极包括通过在形成为大致矩形形状的多个集电体的一个主表面上施加具有正极活性物质或负极活性物质的复合混合物形成的复合混合层， 以及未在长度方向的两端部施加复合混合物的未涂敷部。 一个集电器通过连接部分在纵向方向的一端侧连接到另一个相邻的集电器，复合混合物不连接到该连接部分，连接部分被连续地设置在未施加部件上。 在如上所述构成的电极中，可以层叠多个集电体以获得多层结构，并且可以从仅焊接到集电体的一个端部的引线收集电流。 因此，可以提供具有优异生产率和高容量的新形式的电极。

公开(公告)号：US07399104B2

公开(公告)日：2008-07-15

申请号：US10857768

申请日：2004-05-28

申请人： Margaret Rappaport

发明人： Margaret Rappaport

IPC分类号： F21V17/00

CPC分类号： F21V17/108 ,  F21S8/02 ,  F21V3/00 ,  F21V17/04 ,  F21V17/101 ,  F21V17/105 ,  F21V17/12

摘要： A universal trim piece for a recessed light includes a mounting side disposed toward a ceiling and having an aperture sized to conform with a dimension of an open side of a housing for a recessed light. A decorative side is disposed opposite the mounting side and a universal engagement member, disposed on the mounting side, removably engages a trim ring on the recessed light and secure the universal trim piece to the housing and proximate to the ceiling.

摘要翻译： 用于凹陷光的通用装饰件包括朝向天花板设置的安装侧，其具有尺寸适于与用于凹入光的外壳的开口侧的尺寸相匹配的孔。 装饰侧与安装侧相对设置，并且设置在安装侧的通用接合构件可移除地接合凹入的光线上的装饰环并将通用装饰件固定到壳体并靠近天花板。

公开(公告)号：US07398856B2

公开(公告)日：2008-07-15

申请号：US11211161

申请日：2005-08-24

申请人： Matthew Foster ,  Frank Schwab

发明人： Matthew Foster ,  Frank Schwab

IPC分类号： E04B9/10

CPC分类号： E04B2/7411 ,  E04B2/7457

摘要： The present invention provides an acoustical firewall attenuating assembly. The assembly includes a first frame assembly having a first plate, a second plate and a first plurality of elongate members spaced from one another and extending between the first plate and the second plate. A structure is spaced from the first frame assembly and has an outer surface. A cement wall is positioned between the first frame and the structure and is attached to at least the first frame assembly by a first vibration dampener.

公开(公告)号：US07397507B2

公开(公告)日：2008-07-08

申请号：US10406343

申请日：2003-04-03

申请人： Ken Koseki ,  Tsutomu Haruta ,  Yukihiro Yasui ,  Yasuaki Hisamatsu

发明人： Ken Koseki ,  Tsutomu Haruta ,  Yukihiro Yasui ,  Yasuaki Hisamatsu

IPC分类号： H04N5/16

CPC分类号： H04N5/3575 ,  H04N5/3651 ,  H04N5/378

摘要： An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

摘要翻译： 电流镜70的输入侧的NchMOS晶体管Q71作为电压工作点设定部发挥功能，使得像素信号线电位（水平信号线20的电压）在GND处将保持恒定稳定。 然后，固体摄像装置3的放大晶体管的放大系数和线性度变好。当前的复印机90作为电流采样部分起作用，以便通过电流镜接收固态成像装置3的信号电流IIN 70，在像素信号为电流分量的形状的复位期间中进行像素信号的采样。 计算检测周期中的电流分量与作为采样的复位周期中的当前分量的偏移电流之间的差分允许去除包括在像素信号中的偏移分量，并且仅在 输出端子Iout，从而可以实现FPN抑制功能。

公开(公告)号：US07378695B2

公开(公告)日：2008-05-27

申请号：US11168952

申请日：2005-06-28

申请人： Ikuo Yoshihara

发明人： Ikuo Yoshihara

IPC分类号： H01L31/09

CPC分类号： H01L27/14643 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689

摘要： A solid-state image pickup device is provided in which a pixel forming region 4 and a peripheral circuit forming region 20 are formed on the same semiconductor substrate, a first element isolation portion is formed by an element isolation layer 21 in which an insulating layer is buried into a semiconductor substrate 10 in the peripheral circuit forming region 20, a second element isolation portion is composed of an element isolation region 11 formed within the semiconductor substrate 10 and an element isolation layer 12 projected in the upper direction from the semiconductor substrate 10 in the pixel forming region 4 and an element isolation layer 21 of the first element isolation portion and the element isolation layer 12 of the second element isolation portion contain the same insulating layers 17, 18 and 19. This solid-state image pickup device has a structure capable of suppressing a noise relative to a pixel signal and which can be microminiaturized in the peripheral circuit forming region.

摘要翻译： 提供了一种固态图像拾取装置，其中像素形成区域4和外围电路形成区域20形成在同一半导体衬底上，第一元件隔离部分由元件隔离层21形成，其中绝缘层为 埋设在外围电路形成区域20中的半导体衬底10中，第二元件隔离部分由形成在半导体衬底10内的元件隔离区域11和从半导体衬底10沿上方突出的元件隔离层12组成 第一元件隔离部分的像素形成区域4和元件隔离层21以及第二元件隔离部分的元件隔离层12包含相同的绝缘层17,18和19。 该固态摄像装置具有能够抑制相对于像素信号的噪声并且可以在外围电路形成区域中被微型化的结构。